Simplified output circuit for read only memories

Claim 2

In a memory having a storage matrix of a plurality of rows and a plurality of columns, an input means for selecting a storage location in said storage matrix by row and column and an output means for providing a voltage output representing a logic one or zero stored at said selected storage location, the improvement being said output means which comprises: output switch means for providing a logic one or zero output and having an input; current steering means connected to the output of said storage matrix and said input of said output switch means for controlling the output of said output switch means by steering the current from said storage matrix towards or away from said input of said output switch means; and an enable switch means connected between said output of said storage matrix and a junction of said input to said output switch means and said current steering means for inhibiting or enabling storage matrix current to enter said junction.

Claim 3

In a memory having a storage matrix of a plurality of rows and a plurality of columns of bipolar transistors, an input means for selecting a storage location in said storage matrix by row and column and an output means for providing a voltage output representing a logic one or zero stored at said selected storage location, the improvement being said output means which comprises: an output bipolar transistor having its base connected to an emitter of the plurality of serially connected collector-emitter current path through a selected storage location for providing a logic one or zero output; and current steering means connected to the base of said output transistor for controlling the output of said output transistor by steering the current from said selected storage location towards or away from the base of said output transistor.

Claim 4

In a memory having a storage matrix of a plurality of rows and a plurality of columns of bipolar transistors, an input means for selecting a storage location in said storage matrix by row and column and an output means for providing a voltage output representing a logic one or zero stored at said selected storage location, the improvement being said output means which comprises: an output bipolar transistor having its base connected to an emitter of the plurality of serially connected collector-emitter current path through a selected storage location for providing a logic one or zero output; and current steering means connected to the base of said output transistor for controlling the output of said output transistor by steering the current from said selected storage location towards or away from the base of said output transistor.

Claim 5

A memory output circuit comprising active output switch means having an input terminal to connect said output switch means in series with a memory and its power terminals, to receive current from the selected location in a memory and having an output switching between two voltages as determined by the magnitude of said input current, and current steering means connected to said input terminal for producing distinct switching states of said switch means by steering said input current toward or away from said input terminal of said switch means.

Claim 6

A memory output circuit comprising active output switch means having an input terminal to connect said output switch means in series with a memory and its power terminals, to receive current from the selected location in a memory and having an output switching between two voltages as determined by the magnitude of said input current, and current steering means connected to said input terminal for producing distinct switching states of said switch means by steering said input current toward or away from said input terminal of said switch means.

Claim 7

The memory output circuit of claim 3 wherein said active output switch means comprises a first bipolar transistor having its base as said input terminal and the output being across its collector and emitter.

Claim 8

A memory output circuit comprising an input terminal, a first bipolar transistor output switch having a base to receive current from a selected location in a memory and having an output switching between two voltages as determined by the magnitude of said input current, and an enable switch means having an enable input and connected between said input terminal and said base of said first bipolar transistor for interconnecting said input terminal and said base of said first bipolar transistor in response to an enable signal on said enable input.

Claim 9

A memory output circuit comprising an input terminal, a first bipolar transistor output switch having a base to receive current from a selected location in a memory and having an output switching between two voltages as determined by the magnitude of said input current, and an enable switch means having an enable input and connected between said input terminal and said base of said first bipolar transistor for interconnecting said input terminal and said base of said first bipolar transistor in response to an enable signal on said enable input.

Claim 10

The memory output circuit of claim 5 wherein said enable switch means comprises a second bipolar transistor having its collector-emitter path connected between said input terminal and said base of said first bipolar transistor and its base being said enable input.

Claim 11

A memory output circuit comprising a first bipolar transistor output switch having its base as an input terminal to receive current from a selected location in a memory and having an output switching between two voltages as determined by the magnitude of said input current, and current steering means connected to the base of said first bipolar transistor for producing distinct switching states of said first bipolar transistor by steering said input current toward or away from said base of said first transistor.

Claim 12

A memory output circuit comprising a first bipolar transistor output switch having its base as an input terminal to receive current from a selected location in a memory and having an output switching between two voltages as determined by the magnitude of said input current, and current steering means connected to the base of said first bipolar transistor for producing distinct switching states of said first bipolar transistor by steering said input current toward or away from said base of said first transistor.

Claim 13

The memory output ciruitry of claim 7 wherein said current steering means includes a second bipolar transistor having its collector connected to said base of said first bipolar transistor and its base connected to a biasing source.

Claim 14

The memory output circuit of claim 8 wherein said first and second bipolar transistors are each bipolar Schottky transistors.

Claim 15

In a memory having a storage matrix of a plurality of rows and a plurality of columns, power supply terminals, an input means for selecting a storage location in said storage matrix by row and column and an output means for providing a voltage output representing a logic one or zero stored at said selected storage location, the improvement being said output means which comprises: Output switch means, in series with said storage matrix and said power supply terminals, having an input connected to an output terminal of said storage matrix and switching between two states for providing a logic one or zero output; and current steering means connected to said output terminal of said storage matrix and said input of said output switch means for controlling the switching states of said output switch means by steering the current from said storage matrix towards or away from said input of said output switch means.

Claim 16

In a memory having a storage matrix of a plurality of rows and a plurality of columns, power supply terminals, an input means for selecting a storage location in said storage matrix by row and column and an output means for providing a voltage output representing a logic one or zero stored at said selected storage location, the improvement being said output means which comprises: Output switch means, in series with said storage matrix and said power supply terminals, having an input connected to an output terminal of said storage matrix and switching between two states for providing a logic one or zero output; and current steering means connected to said output terminal of said storage matrix and said input of said output switch means for controlling the switching states of said output switch means by steering the current from said storage matrix towards or away from said input of said output switch means.

Claim 17

The memory of claim 10 wherein said storage matrix includes bipolar transistors, and said output terminal is an emitter of the plural serially connected collector-emitter current path through said selected location.

Claim 18

The memory of claim 10 wherein said storage matrix is a read only memory having a bipolar transistor at each storage location, the collector-emitter path of each bipolar transistor being in series with said output terminal through a storage location.

Claim 19

The memory of claim 10 wherein said output means includes a bipolar transistor having its collector to emitter path connected between said output terminal and a junction of said input to said output switch means and said current steering means and having its base connected to an enable input for enabling or inhibiting the storage matrix current to enter said junction.

Claim 20

The memory of claim 13 wherein said output switch means comprises a bipolar transistor having its base as said input connected to said junction and the output being across its collector-emitter.

Claim 21

The memory of claim 14 wherein said current steering means includes a bipolar transistor having its collector connected to said junction and a biasing circuit connected to its base.

Claim 22

The memory of claim 15 wherein said bipolar transistor of said output switch means and of said current steering means are bipolar Schottky transistors.

Claim 23

In a programmable read only memory having a storage matrix of a plurality of rows and columns, an input means for selecting a storage location in said matrix by row and column and an output means for providing a voltage output representing a logic one or zero stored at said selected storage location, the improvement being said output means which comprises: current sink means connected between an output terminal of said output means and an output terminal of said storage matrix for developing sufficient current through a selected storage location with a first voltage applied to the output terminal of said output means and a second voltage applied to the bias of the storage matrix, which is greater than the normal bias voltage, to cause an open circuit at said selected location; and an enable switch means connected between said output terminal of said storage matrix and the input to said output means for selectively inhibiting storage matrix current from entering said output means.

Claim 24

In a programmable read only memory having a storage matrix of a plurality of rows and columns, an input means for selecting a storage location in said matrix by row and column and an output means for providing a voltage output representing a logic one or zero stored at said selected storage location, the improvement being said output means which comprises: current sink means connected between an output terminal of said output means and an output terminal of said storage matrix for developing sufficient current through a selected storage location with a first voltage applied to the output terminal of said output means and a second voltage applied to the bias of the storage matrix, which is greater than the normal bias voltage, to cause an open circuit at said selected location; and an enable switch means connected between said output terminal of said storage matrix and the input to said output means for selectively inhibiting storage matrix current from entering said output means.

Claim 25

In a programmable read only memory having a storage matrix of a plurality of rows and columns, an input means for selecting a storage location in said matrix by row and column and an output means for providing a voltage output representing a logic one or zero stored at said selected storage location, the improvement being said output means which comprises: current sink means including a transistor having its base connected to an output terminal of said output means and its collector connected to an output terminal of said matrix for developing sufficient current through a selected storage location with a first voltage applied to the output terminal of said output means and a second voltage applied to the bias of the storage matrix, which is greater than the normal bias voltage, to cause an open circuit at said selected location.

Claim 26

In a programmable read only memory having a storage matrix of a plurality of rows and columns, an input means for selecting a storage location in said matrix by row and column and an output means for providing a voltage output representing a logic one or zero stored at said selected storage location, the improvement being said output means which comprises: current sink means including a transistor having its base connected to an output terminal of said output means and its collector connected to an output terminal of said matrix for developing sufficient current through a selected storage location with a first voltage applied to the output terminal of said output means and a second voltage applied to the bias of the storage matrix, which is greater than the normal bias voltage, to cause an open circuit at said selected location.

Claim 27

The programmable read only memory of claim 18 wherein said current sink means further includes a zener diode and resistor connected in series between said base of said transistor and said output terminal of said output means.

Claim 28

The programmable read only memory of claim 18 wherein said storage matrix includes a plurality of bipolar transistors having fusible elements in series with their collector-emitter path between said bias and said output terminal of said storage matrix.