Patent US4076849A successfully refreshed from Google Patents.
US4125832A
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Digital information conversion system
Assignee: Canon Inc
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Filing: 1977-04-12
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Granted: 1978-11-14
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Expires: 1997-04-12
Abstract
Abstract A conversion system for a camera of a type controlled through computation of digital information. The system converts a coded digital value into a digital value of another coding. The code which comprises a gray code representing an integer part of the value and a code pattern representing a decimal part of the value is converted in such a manner that: The integer part is converted into a binary code while the decimal part is converted into a code to which a weight of 1/2, 1/4 or 1/8 is applied. With such a method of conversion employed, values set at 1/3 increment or decrement steps such as ASA film sensitivity values are readily converted into binary codes to facilitate the computing operation of the camera.
Inventors
- 👤 Nobuhiko Shinoda
- 👤 Nobuaki Sakurada
- 👤 Tadashi Ito
- 👤 Masayoshi Yamamichi
- 👤 Hiroyasu Murakami
- 👤 Masayuki Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:58
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/001; G; G03; G03B; G03B7/00; G03B7/08; G03B7/091
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
155 words
A code conversion circuit comprising: (a) a digital information setting means which has a code pattern portion representing a gray-coded integer part and a code pattern portion consisting of first and second bits representing a decimal part varying with 1/3 increment or decrement steps, wherein the code pattern of the first and second bits will have a first code pattern when said integer part represents an odd number, and will have a second code pattern when said integer part represents an even number, while values with 1/3 step variation are set as digital values; and (b) a conversion circuit connected to said digital information setting means, wherein said conversion circuit converts a gray-coded integer part into a binary code representing an integer based on the code of the code pattern portion representing said gray-coded integer part, and converts said decimal part with 1/3 step variation by the code pattern of the first and second bits.
Claim 2
Dependent Claim
155 words
A code conversion circuit comprising: (a) a digital information setting means which has a code pattern portion representing a gray-coded integer part and a code pattern portion consisting of first and second bits representing a decimal part varying with 1/3 increment or decrement steps, wherein the code pattern of the first and second bits will have a first code pattern when said integer part represents an odd number, and will have a second code pattern when said integer part represents an even number, while values with 1/3 step variation are set as digital values; and (b) a conversion circuit connected to said digital information setting means, wherein said conversion circuit converts a gray-coded integer part into a binary code representing an integer based on the code of the code pattern portion representing said gray-coded integer part, and converts said decimal part with 1/3 step variation by the code pattern of the first and second bits.
Claim 3
Dependent Claim
148 words
A code conversion circuit according to claim 1, for converting said gray-coded integer part into binary code and computing a signal for representing a bit of the lowest place in said binary-coded digital value and an exclusive OR of information of said first bit based on said signal representing the bit of the lowest place and said information of first bit, and converting the same into information having a weight of 1/2, also for computing the exclusive OR of the information of said first bit and second bit based on said information of the second bit and converting the same into bit information having a weight of 1/4, and further computing the OR of said bit information having a weight of 1/2 and the bit information having a weight of 1/4 based on said bit information and converting the same into bit information having a weight of 1/8.
Claim 4
Dependent Claim
34 words
A code conversion circuit according to claim 2, which includes an exclusive OR circuit which provides bit information of the lowest place in said binary-coded digital values and the information of the first bit.
Claim 5
Dependent Claim
24 words
A code conversion circuit according to claim 3, which includes an exclusive NOR circuit which supplies the information of said first and second bits.
Claim 6
Dependent Claim
26 words
A code conversion circuit according to claim 4, which includes an OR circuit supplying the outputs of said exclusive OR circuit and the exclusive NOR circuit.
Claim 7
Dependent Claim
150 words
A code conversion circuit according to claim 1, which includes: (a) a circuit which is connected to said information setting means to have said gray-coded integer portion and the information of the first and second bits provided serially; and (b) an information conversion circuit which serially converts the gray-coded information being serially provided into binary code, and at the same time converts the same, together with said information of the first bit, into information having a weight of 1/2 based on the lowest place in said information converted into binary code when said information of the first bit is provided and, further, which converts the same into information having a weight of 1/4 based on the information of the second bit when said second bit information is provided, and also converts the same into information having a weight of 1/8 based on said information having weights of 1/2 and 1/4.
Claim 8
Dependent Claim
67 words
A code conversion circuit according to claim 1, in which the code patterns of the pattern portion consisting of the first and second bits are arranged to progress as "1, 0", "1, 1", "0, 1" when the pattern portion of the gray code represents an odd number, and as "0, 1", "0, 0", "1, 0" when the pattern portion of the gray code represents an even number.
Claim 9
Dependent Claim
67 words
A code conversion circuit according to claim 1, in which the code patterns of the pattern portion consisting of the first and second bits are arranged to progress as "1, 0", "1, 1", "0, 1" when the pattern portion of the gray code represents an odd number, and as "0, 0", "0, 1", "1, 1" when the pattern portion of the gray code represents an even number.
Claim 10
Dependent Claim
212 words
A code conversion circuit comprising: (a) a digital information setting means which has a code pattern portion representing a gray-coded integer part and a code pattern portion consisting of first and second bits representing a decimal part varying with 1/3 increment or decrement steps, wherein the code pattern of the first and second bits will have a first code pattern when said integer part represents an odd number, and will have a second code pattern when said integer part represents an even number, while values with 1/3 step variation are set as digital values; and (b) a conversion circuit which includes: (1) a gray code-binary code conversion circuit which is connected to said setting means and converts code representing gray-coded integer portion into a binary-coded digital value; (2) a first computation circuit which is connected to said setting means and computes an exclusive OR of the above-mentioned information of the first bit and the binary-coded digital value based on the information at the lowest place in said information; (3) a second computation circuit which computes an exclusive NOR of said information of the first and second bits based on said information; and (4) a third computation circuit which is connected to said first and second computation circuits and computes an NOR thereof.
Claim 11
Dependent Claim
212 words
A code conversion circuit comprising: (a) a digital information setting means which has a code pattern portion representing a gray-coded integer part and a code pattern portion consisting of first and second bits representing a decimal part varying with 1/3 increment or decrement steps, wherein the code pattern of the first and second bits will have a first code pattern when said integer part represents an odd number, and will have a second code pattern when said integer part represents an even number, while values with 1/3 step variation are set as digital values; and (b) a conversion circuit which includes: (1) a gray code-binary code conversion circuit which is connected to said setting means and converts code representing gray-coded integer portion into a binary-coded digital value; (2) a first computation circuit which is connected to said setting means and computes an exclusive OR of the above-mentioned information of the first bit and the binary-coded digital value based on the information at the lowest place in said information; (3) a second computation circuit which computes an exclusive NOR of said information of the first and second bits based on said information; and (4) a third computation circuit which is connected to said first and second computation circuits and computes an NOR thereof.
Claim 12
Dependent Claim
194 words
A code conversion circuit comprising: (a) a digital information setting means which has a code pattern portion representing a gray-coded integer part and a code pattern portion consisting of first and second bits representing a decimal part varying with 1/3 increment or decrement steps, wherein the code pattern of the first and second bits will have a first code pattern when said integer part represents an odd number, and will have a second code pattern when said integer part represents an even number, while values with 1/3 step variation are set as digital values; and (b) a conversion circuit, which converts said gray code of code pattern into binary code, and at the same time converts the same into information having a weight of 1/2 based on the lowest place in the information converted into binary code and the information of the first bit, further converts the same into information having a weight of 1/4 based on said information having a weight of 1/2 and said information of the second bit, and also converts the same into information having a weight of 1/8 based on said information having weights of 1/2 and 1/4 respectively.
Claim 13
Dependent Claim
194 words
A code conversion circuit comprising: (a) a digital information setting means which has a code pattern portion representing a gray-coded integer part and a code pattern portion consisting of first and second bits representing a decimal part varying with 1/3 increment or decrement steps, wherein the code pattern of the first and second bits will have a first code pattern when said integer part represents an odd number, and will have a second code pattern when said integer part represents an even number, while values with 1/3 step variation are set as digital values; and (b) a conversion circuit, which converts said gray code of code pattern into binary code, and at the same time converts the same into information having a weight of 1/2 based on the lowest place in the information converted into binary code and the information of the first bit, further converts the same into information having a weight of 1/4 based on said information having a weight of 1/2 and said information of the second bit, and also converts the same into information having a weight of 1/8 based on said information having weights of 1/2 and 1/4 respectively.
Claim 14
Dependent Claim
37 words
A code conversion circuit according to claim 10, which includes a first computation circuit for computing an exclusive OR of said information in the lowest place and the information of the first bit based on said information.
Claim 15
Dependent Claim
33 words
A code conversion circuit according to claim 11, which includes a second computation circuit computing an exclusive OR of said information of the second bit and the output of the first computation circuit.
Claim 16
Dependent Claim
31 words
A code conversion circuit according to claim 12, which includes a third computation circuit computing OR of the outputs of the above-mentioned first and second computation circuits based on said outputs.
References Cited (Backward Citations)
US3728715A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-11-13 | 1982-05-15 | 1982-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-11-13 | 1986-05-15 | 1986-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-11-13 | 1990-05-15 | 1990-11-14 | $7700.00 | Window Closed / Lapsed |