US4123672A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for frequency division of high-frequency pulses
Assignee: US Philips Corp
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Filing: 1977-06-02
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Granted: 1978-10-31
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Expires: 1997-06-02
Abstract
Abstract A circuit arrangement for the frequency division of high frequency pulses in which a cyclic sequence of transistors are connected together via tapped resistances. In integrated circuit technology the tapped resistances may be the parasitic resistance of a semiconductor layer which serves as a common collector for the transistors.
Inventors
- 👤 Wolfdietrich G. Kasperkovitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:58
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/002; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K3/29; H03K5/00; H03K5/00006; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
202 words
A circuit comprising: first and second equal sized groups of transistors, each group having at least one pair of transistors, a cyclic electrical sequence being defined for said transistors, said sequence alternating between said groups so that each of said transistors is followed in said sequence by a transistor of the other group, each of said transistors having a collector, a base and an emitter; a plurality of electrical resistances, each of said resistances connecting the collector of a transistor in said cyclic sequence to the collector of the following transistor in said sequence, each of said electrical resistances having a tapping electrically connected directly to the base of the transistor which preceedes, in said sequence, the pair of transistors between the collectors of which said tapping is disposed; first and second driver transistors, the output from said first driver transistor being electrically connected to each of the emitters of the transistors of said first group, the output from said second driver transistor being electrically connected to each of the emitters of the transistors of said second group; means for alternately driving said first and second driver transistors into conduction; and output means electrically connected to at least one of said tappings.
Claim 2
Dependent Claim
202 words
A circuit comprising: first and second equal sized groups of transistors, each group having at least one pair of transistors, a cyclic electrical sequence being defined for said transistors, said sequence alternating between said groups so that each of said transistors is followed in said sequence by a transistor of the other group, each of said transistors having a collector, a base and an emitter; a plurality of electrical resistances, each of said resistances connecting the collector of a transistor in said cyclic sequence to the collector of the following transistor in said sequence, each of said electrical resistances having a tapping electrically connected directly to the base of the transistor which preceedes, in said sequence, the pair of transistors between the collectors of which said tapping is disposed; first and second driver transistors, the output from said first driver transistor being electrically connected to each of the emitters of the transistors of said first group, the output from said second driver transistor being electrically connected to each of the emitters of the transistors of said second group; means for alternately driving said first and second driver transistors into conduction; and output means electrically connected to at least one of said tappings.
Claim 3
Dependent Claim
202 words
An integrated embodiment of the circuit of claim 1, wherein each of said transistors is a junction transistor, comprising: a semiconductor element including an island of a first conductivity type which island function as the common collector of at least the transistors in said groups; at least four mutually isolated base zones of a second opposite conductivity type disposed in said island in a cyclic physical sequence which corresponds to said electrical sequence with the base zone of each transistor of one group following the base zone of a transistor of the other group; emitter zones of said first conductivity type formed in each of said base zones; conductor means connecting each of said emitter zones in the same group to the collector of the associated driver transistor and further connecting said base zone of each of said transistors in said physical sequence to a tap terminal on said island which is disposed between the next two following base zones in said cyclic physical sequence; said electrical resistances connecting said tap terminals to collector-base depletion layers of said next two following base zones; and further electrical resistances connecting each of said depletion layers to a power supply contact disposed on said island.
Claim 4
Dependent Claim
40 words
A circuit embodiment as claimed in claim 2 further comprising a central terminal which forms said power supply contact and wherein: said base zones are symmetrically disposed around said central terminal; said tap terminals being disposed between said base zones.
Claim 5
Dependent Claim
17 words
A circuit arrangement as claimed in claim 2 wherein said island includes a heavily-doped buried layer therein.
Claim 6
Dependent Claim
24 words
A circuit embodiment as claimed in claim 2 wherein the portions of said island underlying said tap terminals are of said first conductivity type.
Claim 7
Dependent Claim
16 words
A circuit embodiment as claimed in claim 2 wherein an oxide isolation layer surrounds said island.
Claim 8
Dependent Claim
208 words
A circuit for dividing the frequency of high frequency pulses by two, comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a first resistance connecting the collector of said first transistor to the collector of said second transistor and having a first tap connected directly to the base of said fourth transistor; a second resistance connecting the collector of said second transistor to the collector of said third transistor and having a tap connected to the base of said first transistor; a third resistance connecting the collector of said third transistor to the collector of said fourth transistor and having a tap connected to the base of said second transistor; a fourth resistance connecting the collector of said fourth transistor to the collector of said first transistor and having a tap connected to the base of said third transistor; output means connected to at least one of said taps; a fifth transistor having a collector connected to the emitters of said second transistor and of said fourth transistor; a sixth transistor having a collector connected to the emitters of said first transistor and of said third transistor; and means for alternately driving said fifth transistor and said sixth transistor into conduction by said pulses.
Claim 9
Dependent Claim
208 words
A circuit for dividing the frequency of high frequency pulses by two, comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a first resistance connecting the collector of said first transistor to the collector of said second transistor and having a first tap connected directly to the base of said fourth transistor; a second resistance connecting the collector of said second transistor to the collector of said third transistor and having a tap connected to the base of said first transistor; a third resistance connecting the collector of said third transistor to the collector of said fourth transistor and having a tap connected to the base of said second transistor; a fourth resistance connecting the collector of said fourth transistor to the collector of said first transistor and having a tap connected to the base of said third transistor; output means connected to at least one of said taps; a fifth transistor having a collector connected to the emitters of said second transistor and of said fourth transistor; a sixth transistor having a collector connected to the emitters of said first transistor and of said third transistor; and means for alternately driving said fifth transistor and said sixth transistor into conduction by said pulses.
References Cited (Backward Citations)
US3681617A
Cited
US3708691A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-30 | 1982-05-01 | 1982-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-30 | 1986-05-01 | 1986-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-30 | 1990-05-01 | 1990-10-31 | $7700.00 | Window Closed / Lapsed |