Video processor providing sync stripping and reinsertion

Claim 2

A video processor for processing a video input signal provided by a skip-field video tape playback assembly and providing a video output signal having interlaced vertical sync signals, the processor comprising: a video processing circuit connected to the skip-field video tape playback assembly, the video processing circuit receiving the video input signal and interlaced vertical sync pulses, and replacing the vertical sync pulses of the received video input signal with the received interlaced vertical sync pulses to provide the video output signal having interlaced vertical sync pulses; and a sync generator connected to the skip-field video tape playback assembly and to the video processing circuit, the sync generator receiving the video input signal, detecting the vertical sync pulses of the received video input signal and providing the interlaced vertical sync pulses in response to detecting the vertical sync pulses of the received video input signal.

Claim 3

A video processor for processing a video input signal provided by a skip-field video tape playback assembly and providing a video output signal having interlaced vertical sync signals, the video processor comprising: a video processing circuit connected to the skip-field video tape playback assembly, the video processing circuit receiving the video input signal and interlaced vertical sync pulses, and replacing the vertical sync pulses of the received video input signal with the received interlaced vertical sync pulses to provide the video output signal having interlaced vertical sync pulses, comprising: a sync stripper connected to the skip-field video tape playback assembly, the sync stripper receiving the video input signal and stripping the vertical sync pulses from the received video input signal to provide a stripped video signal; and a sync adder connected to the sync stripper, the sync adder receiving the stripped video signal and interlaced vertical sync pulses, and adding the received interlaced vertical sync pulses to the received stripped video signals to provide a video output signal having interlaced vertical sync pulses; and a sync generator connected to the skip-field video tape playback assembly and to the video processing circuit, the sync generator receiving the video input signal, detecting the vertical sync pulses of the received video input signal and providing the interlaced vertical sync pulses in response to detecting the vertical sync pulses of the received video input signal, comprising: a sync separator connected to the skip-field video tape playback assembly, the sync separator receiving the video input signal, detecting the vertical sync pulses of the received video input signal, and providing a vertical sync signal in response to detecting the vertical sync pulses of the received video input signal; a vertical locked oscillator connected to the sync separator, the vertical locked oscillator receiving the vertical sync signal and providing an output signal in phase with the received vertical sync signal; and a vertical sync generator connected to the vertical locked oscillator and to the sync adder, the vertical sync generator receiving the vertical locked oscillator output signal and providing the interlaced vertical sync pulses in response to receiving the vertical locked oscillator output signal.

Claim 4

A video processor for processing a video input signal provided by a skip-field video tape playback assembly and providing a video output signal having interlaced vertical sync signals, the video processor comprising: a video processing circuit connected to the skip-field video tape playback assembly, the video processing circuit receiving the video input signal and interlaced vertical sync pulses, and replacing the vertical sync pulses of the received video input signal with the received interlaced vertical sync pulses to provide the video output signal having interlaced vertical sync pulses, comprising: a sync stripper connected to the skip-field video tape playback assembly, the sync stripper receiving the video input signal and stripping the vertical sync pulses from the received video input signal to provide a stripped video signal; and a sync adder connected to the sync stripper, the sync adder receiving the stripped video signal and interlaced vertical sync pulses, and adding the received interlaced vertical sync pulses to the received stripped video signals to provide a video output signal having interlaced vertical sync pulses; and a sync generator connected to the skip-field video tape playback assembly and to the video processing circuit, the sync generator receiving the video input signal, detecting the vertical sync pulses of the received video input signal and providing the interlaced vertical sync pulses in response to detecting the vertical sync pulses of the received video input signal, comprising: a sync separator connected to the skip-field video tape playback assembly, the sync separator receiving the video input signal, detecting the vertical sync pulses of the received video input signal, and providing a vertical sync signal in response to detecting the vertical sync pulses of the received video input signal; a vertical locked oscillator connected to the sync separator, the vertical locked oscillator receiving the vertical sync signal and providing an output signal in phase with the received vertical sync signal; and a vertical sync generator connected to the vertical locked oscillator and to the sync adder, the vertical sync generator receiving the vertical locked oscillator output signal and providing the interlaced vertical sync pulses in response to receiving the vertical locked oscillator output signal.

Claim 5

The video processor of claim 2 wherein the sync stripper is further characterized as stripping the horizontal sync pulses from the received video input signal; wherein the sync adder is further characterized as receiving horizontal sync pulses and adding the receiving horizontal sync pulses to the received stripped video signal; wherein the sync separator is further characterized as detecting the horizontal sync pulses of the received video input signal and providing a horizontal sync signal in response to detecting the horizontal sync pulses to the received video input signal; and wherein the sync generator is further defined to include: a horizontal locked oscillator connected to the sync separator, the horizontal locked oscillator receiving the horizontal sync signal and providing an output signal in phase with the received horizontal sync signal; and a horizontal sync generator connected to the horizontal locked oscillator and to the sync adder, the horizontal sync generator receiving the horizontal locked oscillator output signal and providing the horizontal sync pulses in response to receiving the horizontal locked oscillator output signal.

Claim 6

The video processor of claim 3 wherein the sync stripper is further characterized as stripping the vertical and horizontal blanking pulses from the received video input signal; wherein the video processing circuit is further defined to include: a blanking adder interposed between the sync stripper and the sync adder, the blanking adder receiving the stripped video signal and vertical and horizontal blanking pulses, and adding the received vertical and horizontal blanking pulses to the received stripped video signal to provide the stripped video signal for application to the sync adder; and wherein the sync generator is further defined to include: a vertical blanking generator connected to the vertical locked oscillator and to the blanking adder, the vertical blanking generator receiving the vertical locked oscillator output signal and providing the vertical blanking pulses in response to receiving the vertical locked oscillator output signal; and a horizontal blanking generator connected to the horizontal locked oscillator and to the blanking adder, the horizontal blanking generator receiving the horizontal locked oscillator output signal and providing the horizontal blanking pulses in response to receiving the horizontal locked oscillator output signal.

Claim 7

The video processor of claim 3 wherein the video input signal is further characterized as being a color video input signal; wherein the sync stripper is further characterized as stripping the color bursts from the received video input signal; wherein the video processing circuit is further defined to include: a burst adder interposed between the blanking adder and the sync adder, the burst adder receiving the stripped video signal from the blanking adder and color bursts, and adding the received color bursts to the received stripped video signal to provide the stripped video signal for application to the sync adder; and wherein the sync generator is further defined to include: a phase locked oscillator connected to the skip-field video tape playback assembly, the phase locked oscillator receiving the video input signal, detecting the color bursts of the received video input signal, and providing an output signal in phase with the detected color bursts of the received video input signal; a burst flag generator connected to the horizontal locked oscillator, the burst flag generator receiving the horizontal locked oscillator output signal and providing burst flags in response to receiving the horizontal locked oscillator output signal; and a burst generator connected to the phase locked oscillator and to the burst flag generator, the burst generator receiving the phase locked oscillator output signal and the burst flags, and providing the color bursts in phase with the received phase locked oscillator output signal in response to receiving each burst flag.