US4121168A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Optically coupled bias circuit for complementary output circuit and method
Assignee: Texas Instruments Tucson Corp
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Filing: 1977-08-24
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Granted: 1978-10-17
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Expires: 1997-08-24
Abstract
Abstract A complementary transistor output circuit and method incorporates an optical coupler including a light emitting diode and a phototransistor connected between the base electrodes of a complementary pair of output transistors including a PNP transistor and an NPN transistor. The emitter of each of the output transistors is connected to an output of the output circuit. The base electrodes of the PNP output transistor and the NPN output transistor are connected, respectively, to first and second current source circuits. The collector electrode of the NPN output transistor is coupled by means of a first feedback circuit including a first resistor and a PNP transistor to the anode of a light emitting diode. The collector electrode of the PNP output transistor is coupled by means of a second feedback circuit to include a second resistor and an NPN transistor to the cathode of the light emitting diode. A phototransistor operates to effectively shunt base drive current supplied by the two current source circuits to the PNP and NPN output transistors to establish a bias voltage, and to maintain a constant quiescent bias current through the output transistors. The magnitude of the quiescent bias current is determined by the resistances of the first and second resistors and by the base-to-emitter voltages of the transistors in the first and second feedback circuits. The method of the invention includes sensing an increase in the bias current in one of the output transistors, increasing the current through the light emitting diode in response to the increase in the bias current, and directing the emitted light to the base of the phototransistor to decrease the bias current.
Inventors
- 👤 Robert M. Stitt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:28
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/34; H03F1/30; H03F3/00; H03F3/04; H03F3/08; H03F3/085; H03F3/30; H03F3/3069; H03F3/3071; H03F3/3072
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
171 words
A complementary transistor output circuit having an output and an input and comprising: (a) a first output transistor of a first conductivity type having first and second electrodes and a control electrode; (b) a second output transistor of a second conductivity type having first and second electrodes and a control electrode, said first electrode of said first transistor being coupled to said first electrode of said second transistor and being also coupled to said output, said input being coupled to said control electrode of both said first and second transistors; and (c) means electrically responsive to an output current component through one of said output transistors and coupling said first and second control electrodes for biasing said first and second output transistors to produce a bias current component in said first and second transistors which is substantially independent of any variations in said output current component through said one of said output transistors, including any variations in said output current caused by temperature variations in said one of said output transistors.
Claim 2
Dependent Claim
171 words
A complementary transistor output circuit having an output and an input and comprising: (a) a first output transistor of a first conductivity type having first and second electrodes and a control electrode; (b) a second output transistor of a second conductivity type having first and second electrodes and a control electrode, said first electrode of said first transistor being coupled to said first electrode of said second transistor and being also coupled to said output, said input being coupled to said control electrode of both said first and second transistors; and (c) means electrically responsive to an output current component through one of said output transistors and coupling said first and second control electrodes for biasing said first and second output transistors to produce a bias current component in said first and second transistors which is substantially independent of any variations in said output current component through said one of said output transistors, including any variations in said output current caused by temperature variations in said one of said output transistors.
Claim 3
Dependent Claim
66 words
The complementary transistor output circuit of claim 1 wherein said biasing means includes an optical coupler responsive to currents in said first and second output transistors and coupled to said first and second control electrodes of said first and second output transistors for reducing a voltage difference between said first and second control electrodes in response to an increase in the magnitude of said bias current.
Claim 4
Dependent Claim
66 words
The output circuit of claim 2 wherein said first output transistor is a PNP output transistor and said second output transistor is an NPN output transistor, the control electrode of each of said output transistors being its base electrode, the first electrode of each of said output transistors being its emitter electrode, and the second electrode of each of said output transistors being its collector electrodes.
Claim 5
Dependent Claim
22 words
The complementary transistor output circuit of claim 3 wherein said input is directly connected to said base of said first output transistor.
Claim 6
Dependent Claim
76 words
The complementary transistor output circuit of claim 4 wherein said optical coupler includes a light emitting diode and a phototransistor positioned with respect to said light emitting diode so that light emitted by said light emitting diode is received by said phototransistor to cause current to flow from the collector of said phototransistor to the emitter of said phototransistor and wherein said phototransistor is coupled between said base electrodes of said first and second output transistors.
Claim 7
Dependent Claim
114 words
The complementary transistor output circuit of claim 5 wherein said biasing means includes first feedback means coupled between the collector of said NPN output transistor and the anode of said light emitting diode for increasing the voltage at said anode of said light emitting diode in response to an increase in the collector current of said NPN transistor, and wherein said complementary transistor output stage further includes second feedback means coupled between the cathode of said light emitting diode and the collector of said PNP output transistor for reducing the voltage of said cathode in response to the increase in the magnitude of the current flowing in the collector of said PNP output transistor.
Claim 8
Dependent Claim
86 words
The complementary transistor output circuit of claim 6 wherein said first feedback means includes a PNP control transistor having its emitter coupled to a positive voltage conductor and its collector connected to said anode of said light emitting diode and its base coupled to the collector of said NPN output transistor, and wherein said second feedback means includes an NPN control transistor having its collector connected to said cathode of said light emitting diode, and its base coupled to the collector of said PNP output transistor.
Claim 9
Dependent Claim
64 words
The complementary transistor output stage of claim 7 further including a first resistor and a pair of series-coupled diodes coupled in parallel between a collector of said NPN output transistor and said positive voltage conductor, and further including a second resistor and a second pair of series-connected diodes coupled in parallel between the collector of said PNP output transistor and a negative voltage conductor.
Claim 10
Dependent Claim
50 words
The complementary transistor output stage of claim 5 further including a compensating capacitor coupled between the base electrodes of said PNP output transistor and said NPN output transistor for producing a relatively large time constant at said base electrodes compared to the period of any signals applied to said input.
Claim 11
Dependent Claim
58 words
The complementary transistor output stage of claim 5 wherein said NPN output transistor is the output transistor of a first Darlington output stage having its input connected to the collector of said phototransistor, and wherein said NPN output transistor is the output transistor of a second Darlington stage having its input connected to the emitter of said phototransistor.
Claim 12
Dependent Claim
89 words
The complementary transistor output circuit of claim 2 further including a first control circuit coupled to the control electrode of said first output transistor for reducing said bias current through said first output transistor in response to an increase in said bias current through said first output transistor, and further including a second control circuit coupled to the control electrode of said second output transistor for reducing said bias current through said second output transistor in response to an increase in said bias current through said second output transistor.
Claim 13
Dependent Claim
27 words
The complementary transistor output stage of claim 1 wherein the magnitude of said bias current is selected to minimize crossover distortion of said complementary transistor output stage.
Claim 14
Independent Claim
194 words
A method of operating a complementary transistor output circuit including a PNP output transistor and an NPN output transistor having their respective emitters connected to a common output, said output circuit including a light emitting diode and a phototransistor, said method including the steps of: (a) producing a bias voltage difference between the base electrodes of said NPN output transistor and said PNP output transistor in order to produce a constant bias current in said NPN and PNP output transistors to reduce crossover distortion of said complementary transistor output circuit; (b) sensing an increase in the bias current in one of said output transistors; (c) directing a current through said light emitting diode; (d) increasing said current through said light emitting diode in response to said increase in said bias current to increase the amount of light emitted by said light emitting diode; (e) directing said emitted light to the base region of said phototransistor to increase the current through said phototransistor; and (f) reducing said bias voltage in response to said increased current through said phototransistor to decrease said bias current, thereby making said complementary transistor output circuit highly resistant to thermal runaway.
Claim 15
Independent Claim
194 words
A method of operating a complementary transistor output circuit including a PNP output transistor and an NPN output transistor having their respective emitters connected to a common output, said output circuit including a light emitting diode and a phototransistor, said method including the steps of: (a) producing a bias voltage difference between the base electrodes of said NPN output transistor and said PNP output transistor in order to produce a constant bias current in said NPN and PNP output transistors to reduce crossover distortion of said complementary transistor output circuit; (b) sensing an increase in the bias current in one of said output transistors; (c) directing a current through said light emitting diode; (d) increasing said current through said light emitting diode in response to said increase in said bias current to increase the amount of light emitted by said light emitting diode; (e) directing said emitted light to the base region of said phototransistor to increase the current through said phototransistor; and (f) reducing said bias voltage in response to said increased current through said phototransistor to decrease said bias current, thereby making said complementary transistor output circuit highly resistant to thermal runaway.
Claim 16
Dependent Claim
231 words
A complementary transistor output circuit including a PNP output transistor and an NPN output transistor having their respective emitter electrodes connected to an output and their base electrodes coupled to an input comprising: a. means coupled between the base electrodes of said PNP output transistor and said NPN output transistors, respectively, for producing a bias voltage difference between the base electrodes of said NPN output transistor and said PNP output transistor in order to produce a constant bias current in said NPN and PNP output transistors to reduce crossover distortion of said complementary transistor output circuit; b. means coupled to the collector of one of said output transistors for sensing an increase in the bias current in said one of said output transistors; c. a light emitting diode; d. a phototransistor coupled between the base electrode of said PNP output transistor and said NPN output transistor, said light emitting diode and said phototransistor being packaged together to form an optical coupler; and e. means coupled to said sensing means and to said light emitting diode for increasing the current through said light emitting diode in response to said increase in said bias current to increase the amount of light emitted by said light emitting diode, thereby increasing the current through said phototransistor and reducing said bias voltage and causing said complementary transistor output circuit to be highly resistant to thermal runaway.
Claim 17
Dependent Claim
231 words
A complementary transistor output circuit including a PNP output transistor and an NPN output transistor having their respective emitter electrodes connected to an output and their base electrodes coupled to an input comprising: a. means coupled between the base electrodes of said PNP output transistor and said NPN output transistors, respectively, for producing a bias voltage difference between the base electrodes of said NPN output transistor and said PNP output transistor in order to produce a constant bias current in said NPN and PNP output transistors to reduce crossover distortion of said complementary transistor output circuit; b. means coupled to the collector of one of said output transistors for sensing an increase in the bias current in said one of said output transistors; c. a light emitting diode; d. a phototransistor coupled between the base electrode of said PNP output transistor and said NPN output transistor, said light emitting diode and said phototransistor being packaged together to form an optical coupler; and e. means coupled to said sensing means and to said light emitting diode for increasing the current through said light emitting diode in response to said increase in said bias current to increase the amount of light emitted by said light emitting diode, thereby increasing the current through said phototransistor and reducing said bias voltage and causing said complementary transistor output circuit to be highly resistant to thermal runaway.
Claim 18
Dependent Claim
179 words
A complementary transistor output circuit having an output and an input and comprising: (a) a first output transistor of a first conductivity type having first and second electrodes and a control electrode; (b) a second output transistor of a second conductivity type having first and second electrodes and a control electrode, said first electrode of said first transistor being coupled to said first electrode of said second transistor and being also coupled to said output, said input being coupled to said control electrode of both said first and second transistors; and (c) first and second current control feedback means responsive to a bias current component flowing through said first and second output transistors, respectively, for controlling the level of said bias current component, said first and second current control feedback means each being further responsive to any output current components in said first and second output transistors, respectively, to cause the other one of said first and second current control feedback means to control said level of said bias current component in both said first and second output transistors.
Claim 19
Dependent Claim
179 words
A complementary transistor output circuit having an output and an input and comprising: (a) a first output transistor of a first conductivity type having first and second electrodes and a control electrode; (b) a second output transistor of a second conductivity type having first and second electrodes and a control electrode, said first electrode of said first transistor being coupled to said first electrode of said second transistor and being also coupled to said output, said input being coupled to said control electrode of both said first and second transistors; and (c) first and second current control feedback means responsive to a bias current component flowing through said first and second output transistors, respectively, for controlling the level of said bias current component, said first and second current control feedback means each being further responsive to any output current components in said first and second output transistors, respectively, to cause the other one of said first and second current control feedback means to control said level of said bias current component in both said first and second output transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-16 | 1982-04-17 | 1982-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-16 | 1986-04-17 | 1986-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-16 | 1990-04-17 | 1990-10-17 | $7700.00 | Window Closed / Lapsed |