US4121166A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase synchronizing circuit for demodulation of multi-phase PSK signals
Assignee: NEC Corp
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Filing: 1977-11-11
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Granted: 1978-10-17
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Expires: 1997-11-11
Abstract
Abstract A phase synchronizing circuit for the demodulation of multi-phase PSK signals has a broadened capture frequency range while avoiding false capture. The circuit includes a phase synchronizing loop having a voltage controlled oscillator for generating a variable frequency output in response to a control voltage and a phase comparator for providing a comparison output representative of the phase difference between the output of the voltage controlled oscillator and an input signal. The comparison output serves as the control voltage for the voltage controlled oscillator. A phase-lock detection circuit is connected to the phase synchronizing loop to detect the phase-synchronized or unsynchronized states of the loop. A low frequency sweep generator is responsive to the phase-lock detection circuit for generating a variable-amplitude voltage which is supplied as a frequency sweep voltage to the voltage controlled oscillator. The frequency sweep voltage is provided for a period of time running from the detection by phase-lock detection circuit of the phase unsynchronized state to a predetermined period of time after the detection of the change from the phase unsynchronized state to the synchronized state.
Inventors
- 👤 Youichi Matsumoto
- 👤 Yoshimi Tagashira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:10
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2272; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/12; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
185 words
In a phase synchronizing circuit for the demodulation of multi-phase PSK signals comprising a phase synchronizing loop, including a voltage controlled oscillator for generating a variable frequency output in response to a control voltage and a phase comparator for providing a comparison output representative of the phase difference between the output of said voltage controlled oscillator and an input signal, said comparison output serving as said control voltage, the improvement wherein said phase synchronizing circuit further comprises: phase synchronization detector means connected to said phase synchronizing loop for detecting the phase-synchronized and unsynchronized states of said loop; low frequency oscillator means connected to receive the output of said phase synchronizing detector means for generating a predetermined variable-amplitude voltage supplied as a frequency sweep voltage for said voltage controlled oscillator during a period of time, said period of time running from the detection at said detector of the phase-unsynchronized state to a predetermined period of time after the detection of the change from the phase-unsynchronized state to the synchronized state; and means for supplying the output of said low frequency oscillator to said phase synchronizing loop.
Claim 2
Dependent Claim
185 words
In a phase synchronizing circuit for the demodulation of multi-phase PSK signals comprising a phase synchronizing loop, including a voltage controlled oscillator for generating a variable frequency output in response to a control voltage and a phase comparator for providing a comparison output representative of the phase difference between the output of said voltage controlled oscillator and an input signal, said comparison output serving as said control voltage, the improvement wherein said phase synchronizing circuit further comprises: phase synchronization detector means connected to said phase synchronizing loop for detecting the phase-synchronized and unsynchronized states of said loop; low frequency oscillator means connected to receive the output of said phase synchronizing detector means for generating a predetermined variable-amplitude voltage supplied as a frequency sweep voltage for said voltage controlled oscillator during a period of time, said period of time running from the detection at said detector of the phase-unsynchronized state to a predetermined period of time after the detection of the change from the phase-unsynchronized state to the synchronized state; and means for supplying the output of said low frequency oscillator to said phase synchronizing loop.
Claim 3
Dependent Claim
63 words
A phase synchronizing circuit as claimed in claim 1 wherein said phase synchronization detector means consists of an oscillator having a predetermined oscillation frequency and means for detecting the level of the oscillation output of said oscillator, said oscillator being connected to said phase synchronizing loop and responsive to the phase-synchronized and unsynchronized states of said loop to stop or start oscillation, respectively.
Claim 4
Dependent Claim
80 words
A phase synchronizing circuit as claimed in claim 2 wherein said low frequency oscillator means comprises a digital circuit, including a reversible counter having its output connected to a D/A converter, said counter receiving as a count input the output of said oscillator, means connected to said counter for periodically reversing the direction of counting, and control means responsive to said means for detecting the level of the oscillation output for inhibiting said counter after said predetermined period of time.
Claim 5
Dependent Claim
136 words
A phase synchronizing circuit as claimed in claim 2 wherein said low frequency oscillator means comprises a second oscillator having a predetermined oscillation frequency which is at least an order of magnitude less than that of the oscillator in said phase synchronization detector means, a control means connected to the output of said second oscillator and responsive to the detection of said unsynchronized state by the output of said means for detecting the level of the oscillation output for passing the output of said second oscillator, and counter means connected to said control means and responsive to the detection of said synchronized state by the output of said means for detecting the level of the oscillation output for causing said control means to block the output of said second oscillator after said predetermined period of time.
Claim 6
Dependent Claim
133 words
A phase synchronizing circuit as claimed in claim 2 wherein said low frequency oscillator means comprises a frequency divider connected to the output of said oscillator and producing an output oscillation frequency which is a sub-multiple of that of said oscillator, a control means connected to the output of said frequency divider and responsive to the detection of said unsynchronized state by the output of said means for detecting the level of the oscillation output for passing the output of said frequency divider, and counter means connected to said control means and responsive to the detection of said synchronized state by the output of said means for detecting the level of the oscillation output for causing said control means to block the output of said frequency divider after said predetermined period of time.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-16 | 1982-04-17 | 1982-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-16 | 1986-04-17 | 1986-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-16 | 1990-04-17 | 1990-10-17 | $7700.00 | Window Closed / Lapsed |