Digital-to-analog converter

Claim 2

A digital to analog converter comprising a serial counter having n - m (where n>m) flip-flops arranged to deliver a first output consisting of m-bits and a second output consisting of n - m bits, means for combining pulses corresponding to said m-bit and (n - m)-bit outputs in weighted fashion to derive an n-bit output, means for filtering said combined pulses to derive a DC output, an AND gate interconnected between the m-th and (m + 1)-th flip-flops of said counter, the output of said m-th flip-flop being connected to one input of said AND gate and the output of said m-th flip-flop being connected to the input of said (m + 1)-th flip-flop, the outputs of the first to m-th flip-flops being connected to the inputs of a first NAND gate and the outputs of the (m + 1)-th to the last flip-flops being connected to the remaining inputs of said NAND gate, the output of said NAND gate being connected to the input of an additional flip-flop, the output of said additional flip-flop being connected to the other input of said AND gate, whereby said m-bit and (n - m)-bit outputs may be alternately derived.

Claim 3

A digital to analog converter as set forth in claim 1 further characterized in that the amplitude A of said (n - m)-bit output and the amplitude B of said m-bit output are so weighted that their ratio may be B/A = 1/2.sup.m.

Claim 4

A digital to analog converter as set forth in claim 1 wherein an output from a first OR gate to which are applied the outputs derived by performing a sequence of logical operations of the outputs from a number of (n - m) flip-flops in said counter and bit signals of an input digital signal applied to (n - m) input terminals, respectively, is derived to provide said (n - m)-bit output, and an output from a second OR gate to which are applied the outputs derived by performing a sequence of logical operations of the outputs from the first to m-th flip-flops in said counter and bit signals of said input digital signal applied to m input terminals, respectively, is derived to provide said m-bit output.

Claim 5

A digital to analog converter according to claim 1, further comprising a first group of outputs from the first to m-th flip-flops in said counter, said first group of outputs being a polarity opposite to that of the outputs applied to said first NAND gate, and a second group of outputs from the m + 1-th to last flip-flops in said counter, said second group of outputs also having a polarity opposite to that of the outputs applied to said first NAND gate, said first and second groups of outputs being coupled to a second NAND gate, the output from said second NAND gate and a pair of outputs of opposite polarity thereto, from said additional flip-flop, being applied to a pair of additional NAND gates, the outputs from said pair of additional NAND gates being applied to the set terminals of a pair of set-reset flip-flops, an output being derived from a first OR gate to provide said (n - m)-bit output, the outputs derived by performing a sequence of logical operations of the outputs from (n - m) flip-flop in said counter and bit signals of an input digital signal applied to a number (n - m) of input terminals, respectively, being applied to said first OR gate, an output being derived from a second OR gate to provide said m-bit output, the outputs derived by performing a sequence of logical operations of the outputs from the first to m-th flip-flops in said counter and bit signals of said input digital signal applied to a number m of input terminals being applied to said second OR gate, and said (n - m)-bit and m-bit outputs being applied to the reset terminals of said pair of set-reset flip-flops, whereby a rectangular waveform signal whose duration encompasses the output pulses from said additional pair of NAND gates, said (n - m)-bit output and said m-bit output may be derived from the output terminals of said pair of set-reset flip-flops.

Claim 6

A digital to analog converter as set forth in claim 4, wherein the output signal from the set-reset flip-flop to which said m-bit output is applied is coupled to the base of a first switching transistor and to a NOR gate, the output signal from the set-reset flip-flop to which said (n - m)-bit output is coupled to said NOR gate, the output signal from said NOR gate is applied to the base of a second switching transistor, the emitters of said first and second switching transistors are grounded, the collector of said first switching transistor is connected through a first resistor to the collector of said second switching transistor, a junction point between said collector of said first switching transistor and said first resistor is coupled to a source of DC voltage through a second resistor and is connected to a smoothing circuit, and R 1 = (2 m - 1) R 2 where R 1 = the value of said second resistor and R 2 = the value of said first resistor.