US4110747A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for producing analog-to-digital conversions
Assignee: BankBoston NA
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Filing: 1976-02-02
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Granted: 1978-08-29
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Expires: 1996-02-02
Abstract
Abstract Analog signals are converted into digital form in a reproducible, accurate and stable manner. The tri-dual phase technique involves the conversion of the condition to be measured, and typically represented by a voltage, first to a reference level and then to an unknown level in a dual phase conversion, and then solving for the unknown level once the relationship of the reference level, the unknown high input level, and the unknown low input levels are established. A circuit capable of carrying out the technique includes an integrator receiving voltage input signals from a switching device adapted to switch to three different input signals, including a high unknown signal level, a low unknown signal level, and a known signal reference level. The reference level is also fed into a comparator which receives the output of the integrator. Calculating circuitry is provided for the output of the comparator for processing the output and presenting the results thereof in a digital display format or other digital output.
Inventors
- 👤 Paul J. LaBrie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 23:15
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/60
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
358 words
Apparatus for converting an unknown analog electronic signal having high and low levels to a digital electronic signal representing a digital measurement of said unknown analog signal, comprising: (a) three input signal terminals for providing a high level of an unknown signal to be measured, a low level of an unknown signal to be measured and a reference signal, (b) timed switch means adapted to connect sequentially to said terminals to produce chopped signals therefrom in predetermined pair combinations, a first pair combination comprised of the high level of the unknown signal and the reference signal, a second pair combination comprised of the low level of the unknown signal and the reference signal, and a third pair combination comprised of the reference signal and the reference signal, (c) electronic integrating means connected to receive signals from said terminals exclusively through said timed switch means, said integrating means being adapted to combine said chopped signals in said predetermined pair combinations, said integrating means generating an integrated signal for each of said pairs, said timed switch means applying said pairs to said integrating means in a predetermined sequence, said timed switch means alternately applying to said integrating means for predetermined periods each signal of each said pair in said predetermined sequence, and (d) comparator means connected to said integrating means and to said reference signal terminal and adapted to provide an output pulse when the amplitude of said integrated signal for each said pair equals said reference signal, (e) counter means connected to said comparator means, said counter means having enabled and disabled states and plural storage means being selectively accessed to store the output of said counter means. (f) pulse means for generating a series of clock pulses, said pulse means connected to said counter means, said counter means counting and storing the number of pulses generated by said pulse means during the integration period for each said pair when enabled, said counter means disabled by said comparator means output pulse, and (g) computer means for processing said counts stored in said storage means, said computer means generating a digital signal representing said unknown analog signal in digital form.
Claim 2
Dependent Claim
358 words
Apparatus for converting an unknown analog electronic signal having high and low levels to a digital electronic signal representing a digital measurement of said unknown analog signal, comprising: (a) three input signal terminals for providing a high level of an unknown signal to be measured, a low level of an unknown signal to be measured and a reference signal, (b) timed switch means adapted to connect sequentially to said terminals to produce chopped signals therefrom in predetermined pair combinations, a first pair combination comprised of the high level of the unknown signal and the reference signal, a second pair combination comprised of the low level of the unknown signal and the reference signal, and a third pair combination comprised of the reference signal and the reference signal, (c) electronic integrating means connected to receive signals from said terminals exclusively through said timed switch means, said integrating means being adapted to combine said chopped signals in said predetermined pair combinations, said integrating means generating an integrated signal for each of said pairs, said timed switch means applying said pairs to said integrating means in a predetermined sequence, said timed switch means alternately applying to said integrating means for predetermined periods each signal of each said pair in said predetermined sequence, and (d) comparator means connected to said integrating means and to said reference signal terminal and adapted to provide an output pulse when the amplitude of said integrated signal for each said pair equals said reference signal, (e) counter means connected to said comparator means, said counter means having enabled and disabled states and plural storage means being selectively accessed to store the output of said counter means. (f) pulse means for generating a series of clock pulses, said pulse means connected to said counter means, said counter means counting and storing the number of pulses generated by said pulse means during the integration period for each said pair when enabled, said counter means disabled by said comparator means output pulse, and (g) computer means for processing said counts stored in said storage means, said computer means generating a digital signal representing said unknown analog signal in digital form.
Claim 3
Dependent Claim
31 words
Apparatus according to claim 1 including programming means connected to said timed switch means and to the output of said comparator means for controlling the operation of said timed switch means.
Claim 4
Dependent Claim
73 words
Apparatus according to claim 2 wherein said counter means includes a counter and said storage means includes register means, said counter connected to the output of said pulse means for counting output pulses therefrom, said register means connected to said counter for separately storing counts from said counter corresponding to the differences between said levels, said computer means connected to said register means for electronically processing the counts stored in said register means.
Claim 5
Dependent Claim
26 words
Apparatus according to claim 3 wherein said pulse means is oscillator means, said oscillator means connected to said counter, said comparator means and said programming means.
Claim 6
Dependent Claim
21 words
Apparatus according to claim 3 including display means connected to said computer means, said digital signal presented on said display means.
Claim 7
Dependent Claim
21 words
Apparatus according to claim 1 wherein said integrating means is a voltage-to-frequency converter and said comparator means is a frequency counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |