US4110746A
Expired / Lapsed
US
⏱️ 0.0 years remaining
A-D converter having nonlinear characteristics
Assignee: Advantest Corp
•
Filing: 1976-06-21
•
Granted: 1978-08-29
•
Expires: 1996-06-21
Abstract
Abstract Disclosed is an A-D converter in which a voltage to be measured is subjected to first integration for a certain period of time; a reference voltage of the opposite polarity from the voltage to be measured is subjected to second integration until the integrated value obtained by the first integration returns to a predetermined value; measuring clock pulses are counted by a counter circuit in the period of the second integration; and the voltage to be measured is converted by the count value of the counter circuit into a digital value. In the A-D converter, there are provided a variable frequency divider and a memory having stored therein frequency dividing ratio determining signals for changing the frequency dividing ratio of the variable frequency divider. In the period of the second integration, the measuring clock pulses are supplied to the counter circuit through the variable frequency divider and each time the clock pulse is obtained, the frequency dividing ratio determining signals are each detected from the memory and preset in the variable frequency divider. And each time the number of clock pulses supplied to the counter circuit exceeds a certain number, the address of the memory is stepped by one. As a result of this, the frequency dividing ratio of the variable frequency divider sequentially changes, by which is obtained a digital converted value conforming to a non-linear characteristic of the voltage to be measured.
Inventors
- 👤 Hikaru Furukawa
- 👤 Masakazu Mitamura
- 👤 Kenji Higuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:56
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/60; H03M1/62; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
231 words
An A-D converter response to an input voltage comprising: integrating means; a source of input voltage; a source of a reference signal opposite in polarity to the input voltage; a reference clock pulse source; a counter; a control logical circuit controlled by the output from the counter to supply the input voltage to the integrating means so that it achieves a first integration until the count value of the counter reaches a preset value from a predetermined one whereafter the integrating means then achieves second integration of the reference signal; a variable frequency divider circuit for frequency dividing the clock pulses from the reference clock pulse source and connected to supply the frequency divided pulses to the counter during the periods of said first and second integrations; an address counter for counting the frequency divided pulses from the frequency divider circuit; a memory having stored therein signals for determining the frequency dividing ratio of the variable frequency divider and addressed in accordance with the count value of the address counter; means for setting in the variable frequency divider one of the frequency dividing ratio determining signals stored in the memory each time a certain number of output pulses are delivered from the variable frequency divider circuit; and means for setting the variable frequency dividing ratio at a fixed frequency dividing ratio other than unity in the period of the first integration.
Claim 2
Dependent Claim
231 words
An A-D converter response to an input voltage comprising: integrating means; a source of input voltage; a source of a reference signal opposite in polarity to the input voltage; a reference clock pulse source; a counter; a control logical circuit controlled by the output from the counter to supply the input voltage to the integrating means so that it achieves a first integration until the count value of the counter reaches a preset value from a predetermined one whereafter the integrating means then achieves second integration of the reference signal; a variable frequency divider circuit for frequency dividing the clock pulses from the reference clock pulse source and connected to supply the frequency divided pulses to the counter during the periods of said first and second integrations; an address counter for counting the frequency divided pulses from the frequency divider circuit; a memory having stored therein signals for determining the frequency dividing ratio of the variable frequency divider and addressed in accordance with the count value of the address counter; means for setting in the variable frequency divider one of the frequency dividing ratio determining signals stored in the memory each time a certain number of output pulses are delivered from the variable frequency divider circuit; and means for setting the variable frequency dividing ratio at a fixed frequency dividing ratio other than unity in the period of the first integration.
Claim 3
Dependent Claim
31 words
The A-D converter according to claim 1, wherein the variable frequency divider circuit is a presettable counter and presets therein the frequency dividing ratio determining signal read out of the memory.
Claim 4
Dependent Claim
87 words
The A-D converter according to claim 1, wherein the variable frequency divider circuit comprises a binary counter, a plurality of selection gates capable of deriving therefrom pulses when a count value of the binary counter corresponds to a plurality of different predetermined values, and an OR gate for obtaining a logical sum of the outputs from the selection gates to provide a frequency divided output pulse, opening and closing of the selection gates being controlled by the frequency dividing ratio determining signal read out of the memory.
Claim 5
Dependent Claim
47 words
The A-D converter according to claim 1, wherein said source of input voltage comprises a thermocouple, said memory having a plurality of memory areas for storing frequency dividing ratio determining signals corresponding to different thermocouple conversion characteristics, and means for selecting between said plurality of memory areas.
Claim 6
Dependent Claim
144 words
The A-D converter according to claim 2 including means for switching the memory to provide a high impedance output or a low impedance output, a fixed frequency dividing ratio signal generator for generating a fixed frequency dividing ratio at all times, said generator being connected to the variable frequency divider circuit, and control means for switching the memory into the high impedance output state in the first integration period to cause the variable frequency divider circuit to serve as a fixed frequency divider circuit having a frequency dividing ratio determined by the fixed frequency dividing ratio signal, and for switching the memory into the low impedance output state in the second integration period to cause the frequency dividing ratio of the variable frequency divider circuit to be determined by the signal read out from the memory regardless of the fixed frequency dividing ratio signal.
References Cited (Backward Citations)
US3662163A
Cited
US3824585A
Cited
US3824379A
Cited
US3824378A
Cited
US3863224A
Cited
US3849635A
Cited
US3939459A
Cited
US4031530A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |