US4110697A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital bypassable register interface
Assignee: United States Department of the Navy
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Filing: 1977-02-22
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Granted: 1978-08-29
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Expires: 1997-02-22
Abstract
Abstract An interface for transmitting data in either a clock edge triggered synchous transmission mode or an asynchronous transmission mode. An edge triggered register has its input connected to a source of digital data and its output connected to a two-to-one multiplexer. A bypass path connected between the digital data source and the multiplexer is provided around the edge triggered register. The two-to-one multiplexer is selectively actuable to provide either asynchronous transmission by connecting the bypass path to an output means or to provide synchronous transmission by connecting the output of the edge triggered register to the output means.
Inventors
- 👤 Dwight R. Wilcox
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:10
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/028; H04L25/029; H03; H03K; H03K5/00; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
105 words
An interface for transmitting data in either a clock edge triggered synchronous transmission mode or an asynchronous tranmission mode comprising: input means for receiving a series of digital data; an edge triggered register connected to said input means and including an input for receiving clock pulses; conducting means connected to said input means for providing a bypass path around said edge triggered register; output means for outputting digital pulses; a two-to-one multiplexer means having inputs connected to said edge triggered register and to said conducting means for selectively connecting the output of either said edge triggered register or said conducting means to said output means.
Claim 2
Dependent Claim
105 words
An interface for transmitting data in either a clock edge triggered synchronous transmission mode or an asynchronous tranmission mode comprising: input means for receiving a series of digital data; an edge triggered register connected to said input means and including an input for receiving clock pulses; conducting means connected to said input means for providing a bypass path around said edge triggered register; output means for outputting digital pulses; a two-to-one multiplexer means having inputs connected to said edge triggered register and to said conducting means for selectively connecting the output of either said edge triggered register or said conducting means to said output means.
Claim 3
Dependent Claim
32 words
The interface of claim 1 wherein said edge triggered register comprises a flip-flop having its data input connected to said input means and having a clock terminal for receiving clock input pulses.
Claim 4
Dependent Claim
87 words
The interface of claim 2 wherein said two-to-one multiplexer means comprises: a first AND gate having a first input thereof connected to said input means and having a second input for connection to a source of digital pulses; a second AND gate having a first input thereof connected to the output of said flip-flop and having a second input for connection to a source of digital pulses; and an OR gate having first and second inputs connected to the output of said first and second AND gates.
Claim 5
Dependent Claim
62 words
The interface of claim 3 wherein said multiplexer further comprises: a first inverter having an input for receiving digital pulses and an output connected to said second input of said first AND gate; and a second inverter having its input connected to the output of said first inverter and having its output connected to said second input of said second AND gate.
Claim 6
Dependent Claim
12 words
The interface of claim 4 wherein said input means comprises a buffer.
Claim 7
Dependent Claim
12 words
The interface of claim 5 wherein said output means comprises a buffer.
Claim 8
Dependent Claim
60 words
The interface of claim 1 wherein said input means comprises a plurality of parallel input terminals each for receiving a series of digital data and wherein said edge triggered register comprises a plurality of flip-flops each having their data input connected to one of said plurality of input terminals and each having a clock terminal for receiving clock input pulses.
Claim 9
Dependent Claim
20 words
The interface of claim 7 wherein said output means comprises a plurality of buffer amplifiers for providing parallel data outputs.
Claim 10
Dependent Claim
126 words
An interface for transmitting data in either a clock edge triggered synchronous transmission mode or an asynchronous transmission mode comprising: input means for receiving a series of digital data; an edge triggered register connected to said input means for receiving said series of digital data, including an input for receiving clock pulses and synchronizing the transmission of said series of digital data therethrough with said clock pulses; conducting means connected to said input means for providing a bypass path around said edge triggered register; output means for outputting digital pulses; a two-to-one multiplexer means having inputs connected to said edge triggered register and to said conducting means for selectively connecting the output of either said edge triggered register or said conducting means to said output means.
Claim 11
Dependent Claim
126 words
An interface for transmitting data in either a clock edge triggered synchronous transmission mode or an asynchronous transmission mode comprising: input means for receiving a series of digital data; an edge triggered register connected to said input means for receiving said series of digital data, including an input for receiving clock pulses and synchronizing the transmission of said series of digital data therethrough with said clock pulses; conducting means connected to said input means for providing a bypass path around said edge triggered register; output means for outputting digital pulses; a two-to-one multiplexer means having inputs connected to said edge triggered register and to said conducting means for selectively connecting the output of either said edge triggered register or said conducting means to said output means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |