US4103308A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital information input method
Assignee: Canon Inc
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Filing: 1976-04-23
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Granted: 1978-07-25
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Expires: 1996-04-23
Abstract
Abstract A plural number of switches which are selectively opened and closed comprise a first switch corresponding with the weight "2/3" in APEX value and a second switch corresponding with the weight "1/3" in APEX value while a n bit register comprises a first bit with the weight "1/2" in APEX value, a second bit with the weight "1/4" in APEX value and a third bit with the weight "1/8" in APEX value. The closing signal of the first switch is put in the first bit, the closing signal of the second switch in the second bit and the closing signal of the third switch in the third bit so as to carry out the approximate conversion of the data.
Inventors
- 👤 Nobuaki Sakurada
- 👤 Masaharu Kawamura
- 👤 Nobuhiko Shinoda
- 👤 Tadashi Ito
- 👤 Hiroyashu Murakami
- 👤 Fumio Ito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:32
CPC Classifications
G; G03; G03B; G03B7/00; G03B7/08; G03B7/091
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
196 words
A digital information input circuit arrangement comprising: a plural number of switches arranged parallel to each other so as to be selectively opened and closed, said plural number of switches including a first switch corresponding to the weight 2/3 in APEX value and a second switch corresponding to the weight 1/3 in APEX value; an n bit register, said register including a first bit with the weight 1/2 in APEX value, a second bit with the weight 1/4 in APEX value and a third bit with the weight 1/8 in APEX value; a signal producing means being connected to the plural number of switches so as to produce closing signals by means of the selective closing of the plural number of switches to be transferred to the register, and a transfer means from transferring to the register the closing signals due to the closing of the plural number of switches, said means including a first transfer means for transferring the closing signal of the first switch to the first bit, the closing signal of the second switch to the second bit and the closing signal of the first and the second switch to the third bit.
Claim 2
Dependent Claim
196 words
A digital information input circuit arrangement comprising: a plural number of switches arranged parallel to each other so as to be selectively opened and closed, said plural number of switches including a first switch corresponding to the weight 2/3 in APEX value and a second switch corresponding to the weight 1/3 in APEX value; an n bit register, said register including a first bit with the weight 1/2 in APEX value, a second bit with the weight 1/4 in APEX value and a third bit with the weight 1/8 in APEX value; a signal producing means being connected to the plural number of switches so as to produce closing signals by means of the selective closing of the plural number of switches to be transferred to the register, and a transfer means from transferring to the register the closing signals due to the closing of the plural number of switches, said means including a first transfer means for transferring the closing signal of the first switch to the first bit, the closing signal of the second switch to the second bit and the closing signal of the first and the second switch to the third bit.
Claim 3
Dependent Claim
20 words
A digital information input circuit arrangement in accordance with claim 1, wherein the third transfer means including an OR gate.
Claim 4
Dependent Claim
35 words
A digital information input circuit arrangement in accordance with claim 2 wherein the signal producing means includes a current source and resistances provided between the current source and each of the plural number of switches.
Claim 5
Dependent Claim
229 words
A digital information input circuit arrangement comprising: a plural number of switches arranged parallel to each other so as to be selectively opened and closed, said plural number of switches including a first switch corresponding to the weight 2/3 of an APEX value and a second switch corresponding to the weight 1/3 in APEX value; an a bit register, said register including a first bit with the weight 1/2 in APEX value, a second bit with the weight 1/4 in APEX value and a third bit with the weight 1/8 in APEX value; an n bit counter for successively producing timing pulses, said counter including a first bit for producing a pulse by the closing of the first switch for the register, a second bit producing a pulse by the closing of the second switch for the register and a third bit always producing pulses for the register; and a transfer means for transferring the pulses from the counter to the register, said means including a first transfer means for transferring to the register the pulses by means of the closing of the plural number of switches and a second transfer means for transferring the pulse from the third bit of the counter to the register, said second transfer means presenting a means for detecting the pulse by means of the closing of the first or the second switch.
Claim 6
Dependent Claim
229 words
A digital information input circuit arrangement comprising: a plural number of switches arranged parallel to each other so as to be selectively opened and closed, said plural number of switches including a first switch corresponding to the weight 2/3 of an APEX value and a second switch corresponding to the weight 1/3 in APEX value; an a bit register, said register including a first bit with the weight 1/2 in APEX value, a second bit with the weight 1/4 in APEX value and a third bit with the weight 1/8 in APEX value; an n bit counter for successively producing timing pulses, said counter including a first bit for producing a pulse by the closing of the first switch for the register, a second bit producing a pulse by the closing of the second switch for the register and a third bit always producing pulses for the register; and a transfer means for transferring the pulses from the counter to the register, said means including a first transfer means for transferring to the register the pulses by means of the closing of the plural number of switches and a second transfer means for transferring the pulse from the third bit of the counter to the register, said second transfer means presenting a means for detecting the pulse by means of the closing of the first or the second switch.
References Cited (Backward Citations)
DE2538144A1
Cited
US4037233A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-24 | 1982-01-23 | 1982-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-24 | 1986-01-23 | 1986-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-24 | 1990-01-23 | 1990-07-25 | $7700.00 | Window Closed / Lapsed |