US4101882A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data read-out system and apparatus useful for angular measurements
Assignee: Brunton Co
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Filing: 1976-05-28
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Granted: 1978-07-18
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Expires: 1996-05-28
Abstract
Abstract Data acquired from a source such as a coded disc is processed so as to be free of ambiguities associated with boundary transitions where the data source produces groups of bits which have least significant ordering and higher significant ordering. Wherever a common transition boundary between the bit groups occurs, ambiguities from misalignment of these boundaries are avoided by controlling the higher ordered bit transitions from the lower ordered bit transitions. Circuitry tracks and stores the higher order bits by synchronous updating whenever no misalignment or skew sensitive transitions are encountered. Logic circuitry continuously inspects the lower significant bits to determine the presence or absence of a zone surrounding the common transition boundary and also detects the actual passage and direction of the transition boundary in the lower significant bit group. This logic corrects the counter stored higher order bit counts in conformity with the status of the lower significant bit states. The system output is a composite of the lower significant digits read directly and the controlled and updated higher significant digits with appropriate code conversion. Whenever the data source is an optical coded disc or the like, the data acquired can be enhanced by an arrangement of light collimating and focusing elements relative to the coded transparent/opaque areas of the disc cell tracks.
Inventors
- 👤 Melvin G. Kramer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:08
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/22; H03M1/24; H03M1/28; H03M1/287
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
220 words
In a system having an input of a group of least significant bits and one or more groups of higher significant bits which change state at one transition point of one of the least significant bits, apparatus for producing output date correlated to the system input free of transition ambiguities comprising: system output means; means for coupling information correlated to the least significant bits to said system output means; means for storing information correlated to the higher significant bits and for transferring said stored information to said system output means; control circuit means responsive to the status of the least significant bits for controlling the information input into said storage means, said control circuit means generating a control signal in the presence of a first zone around the transition point and a transition reflecting signal in the presence of the transition point, said control circuit generating a load signal in the presence of a second zone removed from said first zone, said load signal operative to input higher significant bit correlated information into said storage means; and commutation circuit means associated with said control circuit means and responsive to said control signal for disabling said storage means from receiving said higher significant bit correlated information and responsive to said transition reflecting signal for altering the information in said storage means.
Claim 2
Dependent Claim
220 words
In a system having an input of a group of least significant bits and one or more groups of higher significant bits which change state at one transition point of one of the least significant bits, apparatus for producing output date correlated to the system input free of transition ambiguities comprising: system output means; means for coupling information correlated to the least significant bits to said system output means; means for storing information correlated to the higher significant bits and for transferring said stored information to said system output means; control circuit means responsive to the status of the least significant bits for controlling the information input into said storage means, said control circuit means generating a control signal in the presence of a first zone around the transition point and a transition reflecting signal in the presence of the transition point, said control circuit generating a load signal in the presence of a second zone removed from said first zone, said load signal operative to input higher significant bit correlated information into said storage means; and commutation circuit means associated with said control circuit means and responsive to said control signal for disabling said storage means from receiving said higher significant bit correlated information and responsive to said transition reflecting signal for altering the information in said storage means.
Claim 3
Dependent Claim
87 words
Apparatus in accordance with claim 1 wherein said control circuit means includes means for producing a first transition reflecting signal when the transition point is passed in a first direction and a second transition reflecting signal when the transition point is passed in an opposite direction, said commutation circuit means including means operable in the presence of said control signal for incrementing said stored information in response to said first transition reflecting signal and for decrementing said stored information in response to said second transition reflecting signal.
Claim 4
Dependent Claim
70 words
Apparatus in accordance with claim 1 which includes an enabling signal means operable during a predetermined time span after initial start-up of the system for preventing said storage means from transfering any said information until after receiving at least one said higher significant bit correlated information, said enabling signal means coupled to said least significant bits in a region not corresponding to said transition point of said higher significant bits.
Claim 5
Dependent Claim
42 words
Apparatus in accordance with claim 1 wherein said system output means includes a plurality of display devices connected for receiving respective outputs from said coupling means and said storing means for providing separate displays correlated to respective groups of system input bits.
Claim 6
Dependent Claim
283 words
In a system having an input of a plurality of groups of binary bits with a first of the groups corresponding to a least significant order of information and one or more of the other groups corresponding to higher significant orders of information correlated to the least significant order group and wherein a first of the least significant bits changes binary state at points where at least one of the higher ordered groups changes binary state and a second of the least significant bits has a constant first binary state at the first bit binary state change point and a constant second binary state between the first bit binary state change points, apparatus for producing accurate output information comprising: a plurality of output terminals, means responsive to the first group of binary bits for coupling the information thereof to said output terminals, counter circuit means having an output relfective of the contents thereof and operable in a first mode for conforming said contents in response to signals at a first input thereof and in a second mode for changing the state of said contents in response to signals at a second input thereof, means responsive to the higher significant order group bits for coupling the information thereof to said counter circuit means first input, commutation means responsive to the first and second binary states of the second least significant bit for enabling said counter circuit means for said second and first mode operation, respectively, control means responsive to a binary state change of the first least significant bit for introducing an input signal to said counter circuit means second input, and means for connecting said counter circuit means output to said output terminals.
Claim 7
Dependent Claim
283 words
In a system having an input of a plurality of groups of binary bits with a first of the groups corresponding to a least significant order of information and one or more of the other groups corresponding to higher significant orders of information correlated to the least significant order group and wherein a first of the least significant bits changes binary state at points where at least one of the higher ordered groups changes binary state and a second of the least significant bits has a constant first binary state at the first bit binary state change point and a constant second binary state between the first bit binary state change points, apparatus for producing accurate output information comprising: a plurality of output terminals, means responsive to the first group of binary bits for coupling the information thereof to said output terminals, counter circuit means having an output relfective of the contents thereof and operable in a first mode for conforming said contents in response to signals at a first input thereof and in a second mode for changing the state of said contents in response to signals at a second input thereof, means responsive to the higher significant order group bits for coupling the information thereof to said counter circuit means first input, commutation means responsive to the first and second binary states of the second least significant bit for enabling said counter circuit means for said second and first mode operation, respectively, control means responsive to a binary state change of the first least significant bit for introducing an input signal to said counter circuit means second input, and means for connecting said counter circuit means output to said output terminals.
Claim 8
Dependent Claim
77 words
Apparatus in accordance with claim 5 wherein said control means includes means introducing a first input signal to said counter circuit means whenever the first least significant bit changes binary state in a first direction and a second input signal whenever the first least significant bit changes binary state in an opposite direction, said counter circuit means in said second mode responding to said first and second input signals by respectively incrementing and decrementing said contents thereof.
Claim 9
Dependent Claim
55 words
Apparatus in accordance with claim 5 which includes a source of periodic pulses, storage means responsive to said periodic pulses for receiving and storing the binary bit groups, and connecting circuit means for introducing the content of said storage means to the input of said coupling means and to said counter circuit means first input.
Claim 10
Dependent Claim
75 words
Apparatus in accordance with claim 7 wherein said connecting circuit means includes gate circuit means, said apparatus further including means operable in response to initial start-up of the system for introducing an enabling signal to said gate circuit means a predetermined time period thereafter for allowing said storage means to store at least one set of groups of binary bits during a period that the second least significant bit it in the second binary state.
Claim 11
Dependent Claim
46 words
Apparatus in accordance with claim 8 wherein said commutation means and said control means are inoperative until enabled by said initial start-up enabling signal, said enabling signal coupled to said least significant bits in a region removed from the transition points of said higher order groups.
Claim 12
Dependent Claim
39 words
Apparatus in accordance with claim 5 which includes a plurality of display devices connected to respective groups of said plurality of output terminals for providing indications of information corresponding to the groups of binary bits at the system input.
Claim 13
Dependent Claim
52 words
Apparatus in accordance with claim 10 which includes a source of operating power connected to energize said apparatus, means for detecting that the operating power from said source is below an acceptable level, and means responsive to said detecting means for causing said display devices to reflect the unacceptable power level condition.
Claim 14
Independent Claim
434 words
A system for providing accurate information concerning the angular displacement of a body relative to a reference line comprising: a disc mounted for accommodating rotary motion thereof relative to the body and having a plurality of radial tracks each having a plurality of groups of cells with said cells containing coded information corresponding to angular displacement from the reference line, said groups in each track including a first group having bits corresponding to a least significant digit with a first bit of said first group changing binary state at a transition boundary and a second bit of said first group having a first binary state for a zone around said transition boundary and a second binary state outside said zone, at least one of the other said groups having cells corresponding to a higher significant digit with the binary state of one cell thereof changing at said transition boundary, a plurality of means fixed relative to the body for sensing the binary state of said cells of each said track, a plurality of data latches connected to receive the outputs of respective said sensing means, a plurality of gate circuits, means interconnecting said data latch outputs to respective said gate circuits, a source of repetitively cycling sequential pulses, said data latches being responsive to a first said pulse for storing the outputs of said sensing means, timing circuit means responsive to the initial said first pulse after start-up of the system for producing a continuous output signal a predetermined time thereafter for enabling said plurality of gate circuits, commutation circuit means coupled for receiving the outputs of said data latches corresponding to the binary state of said first and second least significant bits and for producing first control signals outside of said zone, said commutation circuit being responsive to a second said sequential pulse for producing second control signals in the presence of said zone and the change in binary state of said least significant group first bit, counter circuit means having a first input coupled to the outputs of said gate circuits corresponding to said higher significant bits and a second input coupled to said commutation circuit means control signals, said counter circuit means responding to said first control signal by conforming the contents thereof to said first counter circuit means input and to said second control signals by ignoring said first input thereof and by changing the contents thereof when said first bit binary state changes, and output circuit means interconnected for receiving said gate circuit means outputs corresponding to said least significant group and the output of said counter circuit means.
Claim 15
Independent Claim
434 words
A system for providing accurate information concerning the angular displacement of a body relative to a reference line comprising: a disc mounted for accommodating rotary motion thereof relative to the body and having a plurality of radial tracks each having a plurality of groups of cells with said cells containing coded information corresponding to angular displacement from the reference line, said groups in each track including a first group having bits corresponding to a least significant digit with a first bit of said first group changing binary state at a transition boundary and a second bit of said first group having a first binary state for a zone around said transition boundary and a second binary state outside said zone, at least one of the other said groups having cells corresponding to a higher significant digit with the binary state of one cell thereof changing at said transition boundary, a plurality of means fixed relative to the body for sensing the binary state of said cells of each said track, a plurality of data latches connected to receive the outputs of respective said sensing means, a plurality of gate circuits, means interconnecting said data latch outputs to respective said gate circuits, a source of repetitively cycling sequential pulses, said data latches being responsive to a first said pulse for storing the outputs of said sensing means, timing circuit means responsive to the initial said first pulse after start-up of the system for producing a continuous output signal a predetermined time thereafter for enabling said plurality of gate circuits, commutation circuit means coupled for receiving the outputs of said data latches corresponding to the binary state of said first and second least significant bits and for producing first control signals outside of said zone, said commutation circuit being responsive to a second said sequential pulse for producing second control signals in the presence of said zone and the change in binary state of said least significant group first bit, counter circuit means having a first input coupled to the outputs of said gate circuits corresponding to said higher significant bits and a second input coupled to said commutation circuit means control signals, said counter circuit means responding to said first control signal by conforming the contents thereof to said first counter circuit means input and to said second control signals by ignoring said first input thereof and by changing the contents thereof when said first bit binary state changes, and output circuit means interconnected for receiving said gate circuit means outputs corresponding to said least significant group and the output of said counter circuit means.
Claim 16
Dependent Claim
88 words
A system in accordance with claim 12 wherein said counter circuit means includes an up/down counter, said commutation circuit means including means detecting the direction of binary state changes of said least significant digit first bit for producing an up count for said second control signal for a first said state change direction and a down count for said second control signal for the opposite said direction, said up/down counter responding to said up and down count second control signals by respectively incrementing and decrementing the contents thereof.
Claim 17
Dependent Claim
43 words
A system in accordance with claim 13 wherein said disc is coded in excess-3 Gray code, said up/down counter is a binary up/down counter, and said data latch to gate circuit interconnecting means includes an excess-3 Gray code to binary code converter circuit.
Claim 18
Dependent Claim
69 words
A system in accordance with claim 14 wherein said commutation circuit direction detecting means includes a latch circuit, means responsive to said second sequential pulse for comparing said latch circuit state with the state of said least significant digit first bit, and means responsive to a third said sequential pulse for conforming the state of said latch circuit to the current status of said least significant digit first bit.
Claim 19
Dependent Claim
40 words
A system in accordance with claim 12 wherein said timing circuit means produces said continuous output signal only after the concurrence of a first said sequential pulse and a signal from said sensing means indicating said zone is not present.
Claim 20
Dependent Claim
40 words
A system in accordance with claim 16 which includes means responsive to initial system start-up for causing sufficient relative motion between said disc and said sensing means for insuring that said first group bits will occur outside of said zone.
Claim 21
Dependent Claim
80 words
A system in accordance with claim 12 wherein said disc cells are coded as transparent or opaque areas, said sensing means includes a plurality of light emitting devices arrayed in conformity to said radial tracks on one side of said disc and a plurality of light sensitive devices arrayed on the opposite side of said disc for receiving light originating from respective said emitting devices and passing through said disc for producing electrical output signals corresponding to said received light.
Claim 22
Dependent Claim
58 words
A system in accordance with claim 18 wherein said sequential pulse source produces a low duty cycle enabling pulse for energizing said light emitting devices, said first sequential pulse from said source being produced subsequent to the initiation of but concurrently with said enabling pulse for insuring that said light sensitive device electrical output signals have been stabilized.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-17 | 1982-01-16 | 1982-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-17 | 1986-01-16 | 1986-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-17 | 1990-01-16 | 1990-07-18 | $7700.00 | Window Closed / Lapsed |