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US4099264A
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Non-destructive interrogation control circuit for a variable threshold FET memory
Assignee: Unisys Corp
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Filing: 1976-10-28
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Granted: 1978-07-04
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Expires: 1996-10-28
Abstract
Abstract An illustrative embodiment of the invention provides a substantially non-destructive interrogation circuit for a memory cell such as a variable threshold insulated gate field effect memory transistor device whereby the circuit generates a fixed current for interrogation of the memory transistor such that the disturb voltage, the voltage impressed across the insulator of the memory transistor during interrogation, is minimized and is a function of the current and the gain of the memory device and not the threshold of the memory device. Moreover the disturb voltage is readily calculable and is equal for all interrogations and, therefore, enables one to calculate the maximum number of interrogations of a memory cell before the disturb voltage destroys the memory threshold of the memory cell and rewriting of the data therein must be performed. In addition, a sense latch circuit provides means for sensing the memory data of the memory cell without applying an additional disturb potential to the device.
Inventors
- 👤 Robert J. Lodi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:08
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
74 words
A method of interrogating a variable threshold field effect transistor comprising the steps of, coupling an electrode of a field effect transistor to one electrode of the variable threshold field effect transistor, biasing the gate and other electrodes of said variable threshold field effect transistor, and biasing the gate electrode of said field effect transistor with a fixed on drive voltage for generating a constant current to interrogate said variable threshold field effect transistor.
Claim 2
Independent Claim
74 words
A method of interrogating a variable threshold field effect transistor comprising the steps of, coupling an electrode of a field effect transistor to one electrode of the variable threshold field effect transistor, biasing the gate and other electrodes of said variable threshold field effect transistor, and biasing the gate electrode of said field effect transistor with a fixed on drive voltage for generating a constant current to interrogate said variable threshold field effect transistor.
Claim 3
Dependent Claim
79 words
A memory device of the type having a memory cell comprising, a field effect transistor coupled in series with said memory cell for applying a current signal thereto, and a control voltage source coupled to the gate of said field effect transistor for providing a control voltage thereto, said control voltage increasing or decreasing directly with changes in the threshold voltage of said field effect transistor thereby providing a fixed on drive voltage for maintaining the current signal constant.
Claim 4
Dependent Claim
79 words
A memory device of the type having a memory cell comprising, a field effect transistor coupled in series with said memory cell for applying a current signal thereto, and a control voltage source coupled to the gate of said field effect transistor for providing a control voltage thereto, said control voltage increasing or decreasing directly with changes in the threshold voltage of said field effect transistor thereby providing a fixed on drive voltage for maintaining the current signal constant.
Claim 5
Dependent Claim
21 words
A memory device according to claim 2, further including a sense latch circuit coupled to the output of the memory cell.
Claim 6
Dependent Claim
73 words
A memory device according to claim 3 wherein said sense/latch circuit includes a plurality of field effect transistors cross coupled in a latching configuration, said cross coupled transistors each having an output, the output of the variable threshold transistor device being coupled between the output and an electrode of one of the cross coupled transistors, and a reference voltage being coupled between the output and an electrode of the other cross coupled transistor.
Claim 7
Dependent Claim
21 words
A memory device according to claim 2, wherein said control voltage source includes a plurality of fixed threshold field effect transistors.
Claim 8
Dependent Claim
21 words
A memory device according to claim 5 wherein said field effect transistor comprises a fixed threshold insulated gate field effect transistors.
Claim 9
Dependent Claim
47 words
A memory device according to claim 5 wherein said control voltage source includes a first pair of field effect transistors connected in series as a voltage divider providing a fixed output therebetween coupled to a second pair of field effect transistors for providing the control voltage therefrom.
Claim 10
Dependent Claim
20 words
A memory device according to claim 7 wherein said memory cell comprises a variable threshold insulated gate field effect transistor.
Claim 11
Dependent Claim
23 words
A memory device according to claim 7 wherein said field effect transistors comprise insulated gate field effect transistors fabricated on a single chip.
Claim 12
Dependent Claim
40 words
A memory device according to claim 7 wherein the first pair of field effect transistors have a gain ratio of one and the second pair of field effect transistors have a gain ratio (K 38 /K 36 ) of four.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-03 | 1982-01-02 | 1982-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-03 | 1986-01-02 | 1986-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-03 | 1990-01-02 | 1990-07-04 | $7700.00 | Window Closed / Lapsed |