US4097812A
Expired / Lapsed
US
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Frequency selective detector circuit
Assignee: Panasonic Holdings Corp
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Filing: 1977-07-25
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Granted: 1978-06-27
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Expires: 1997-07-25
Abstract
Abstract A frequency selective detector circuit is useful as a high/low pass detector or as a bandpass detector. The high/low pass detector comprises a pair of digital missing pulse detector circuits or resettable one-shot multivibrators that are connected together in cascade between a source of input pulses and the detector circuit output. The timing interval of the first missing pulse detector circuit in the cascade is less than the timing interval of the second missing pulse detector circuit in the cascade. By combining two such circuits to supply their outputs to a coincidence gate, a bandpass detector circuit results.
Inventors
- 👤 Theodore S. Rzeszewski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:37
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/02; G01R23/15; G08; G08C; G08C19/00; G08C19/12; H; H03; H03D; H03D3/00; H03D3/02; H03D3/18; H03D3/20; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/156; H04L27/1563; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/446; H04Q1/448
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
181 words
A frequency selective detector system including in combination: first means having an input and an output for measuring an interval between pulses applied to the input thereof and providing a first output state on the output thereof when the interval between such input pulses is less than a first predetermined amount and providing a second output state on the output thereof whenever the interval between such input pulses is more than said first predetermined amount; second means having an input connected to the output of said first means for measuring an interval between input pulses applied thereto and responsive to the output state of said first means to provide a first output state on the output thereof whenever the interval between successive attainments of the second output state of said first means is less than a second predetermined amount and providing a second output state whenever the time interval between successive attainments of the second output state of said first means is more than said second predetermined amount; and means for supplying input pulses to the input of said first means.
Claim 2
Dependent Claim
181 words
A frequency selective detector system including in combination: first means having an input and an output for measuring an interval between pulses applied to the input thereof and providing a first output state on the output thereof when the interval between such input pulses is less than a first predetermined amount and providing a second output state on the output thereof whenever the interval between such input pulses is more than said first predetermined amount; second means having an input connected to the output of said first means for measuring an interval between input pulses applied thereto and responsive to the output state of said first means to provide a first output state on the output thereof whenever the interval between successive attainments of the second output state of said first means is less than a second predetermined amount and providing a second output state whenever the time interval between successive attainments of the second output state of said first means is more than said second predetermined amount; and means for supplying input pulses to the input of said first means.
Claim 3
Dependent Claim
103 words
A frequency selective detector circuit including in combination: a first digital missing pulse detector circuit with an input terminal and an output terminal and having a first predetermined timing interval; a second digital missing pulse detector circuit having an input terminal and an output terminal, the input terminal of said second missing pulse detector circuit being connected with the output terminal of said first missing pulse detector circuit, said second missing pulse detector circuit having a second predetermined timing interval greater than said first predetermined timing interval; and means for supplying input pulses to the input of said first missing pulse detector circuit.
Claim 4
Dependent Claim
103 words
A frequency selective detector circuit including in combination: a first digital missing pulse detector circuit with an input terminal and an output terminal and having a first predetermined timing interval; a second digital missing pulse detector circuit having an input terminal and an output terminal, the input terminal of said second missing pulse detector circuit being connected with the output terminal of said first missing pulse detector circuit, said second missing pulse detector circuit having a second predetermined timing interval greater than said first predetermined timing interval; and means for supplying input pulses to the input of said first missing pulse detector circuit.
Claim 5
Dependent Claim
145 words
The combination according to claim 2 further including third and fourth missing pulse detector circuits each having an input terminal and an output terminal; means connecting the input terminal of said third missing pulse detector circuit in common with the input terminal of said first missing pulse detector circuit, said third missing pulse detector circuit having a third predetermined timing interval different from said first predetermined timing interval of said first missing pulse detector circuit; and the input terminal of said fourth missing pulse detector circuit being connected with the output terminal of said third missing pulse detector circuit, said fourth missing pulse detector circuit having a fourth predetermined time interval greater than said third predetermined time interval; and coincidence gate means connected to the outputs of said second and fourth missing pulse detector circuit for producing the output of the frequency selective detector circuit.
Claim 6
Dependent Claim
66 words
The combination according to claim 3 wherein said coincidence gating means comprises a coincidence gate circuit and an inverter, and the output of one of said second and fourth missing pulse detector circuits is applied directly to said coincidence gate circuit and the output of the other of said second and fourth missing pulse detector circuits is applied through said inverter to said coincidence gate circuit.
Claim 7
Dependent Claim
30 words
The combination according to claim 3 wherein the timing interval of said third missing pulse detector circuit is less than the timing interval of said first missing pulse detector circuit.
Claim 8
Dependent Claim
35 words
The combination according to claim 5 wherein the timing intervals of said second and fourth missing pulse detector circuits are substantially greater than the timing intervals of said first and third missing pulse detector circuits.
Claim 9
Dependent Claim
21 words
The combination according to claim 6 wherein the timing intervals of said second and fourth missing pulse detector circuits are equal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-26 | 1981-12-26 | 1982-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-26 | 1985-12-26 | 1986-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-26 | 1989-12-26 | 1990-06-27 | $7700.00 | Window Closed / Lapsed |