US4097771A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated clock pulse shaper
Assignee: ITT Inc
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Filing: 1976-12-28
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Granted: 1978-06-27
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Expires: 1996-12-28
Abstract
Abstract An integrated clock pulse shaper showing a pair of resistivities each of which is connected in series to ground over the source drain line of one of a pair of MISFETs. The MISFETs are galvanically cross-coupled from the drain to the gate. A pair of overlapping pulse trains each of which is fed to one of the pair of resistivities, are shaped to a non-overlapping pair of pulse trains occurring at the common connection points of each transistor/resistivity pair.
Inventors
- 👤 Wolfgang Gollinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:01
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K5/1515; H03K3/00; H03K3/02; H03K3/353; H03K3/356
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
125 words
An integrated clock pulse shaper for providing first and second non-overlapping clock signal voltages for use in multiphase clocked logic circuits, comprising: a first insulated-gate field effect transistor having source, drain and gate terminals; a second insulated-gate field effect transistor having source, drain and gate terminals, the drain terminal of each of said first and second transistors galvanically cross coupled to the gate terminals of said second and first transistor respectively; a first resistor; a second resistor; and means for applying first and second clock signal voltages to the source drain paths of said first and second transistors respectively via said first and second resistors, said first and second non-overlapping clock signal voltages appearing at the drain terminals of said first and second transistors respectively.
Claim 2
Dependent Claim
125 words
An integrated clock pulse shaper for providing first and second non-overlapping clock signal voltages for use in multiphase clocked logic circuits, comprising: a first insulated-gate field effect transistor having source, drain and gate terminals; a second insulated-gate field effect transistor having source, drain and gate terminals, the drain terminal of each of said first and second transistors galvanically cross coupled to the gate terminals of said second and first transistor respectively; a first resistor; a second resistor; and means for applying first and second clock signal voltages to the source drain paths of said first and second transistors respectively via said first and second resistors, said first and second non-overlapping clock signal voltages appearing at the drain terminals of said first and second transistors respectively.
Claim 3
Dependent Claim
33 words
An integrated clock pulse shaper according to claim 1 further including first and second reversely biased pn-diodes coupled between the drain terminals of said first and second transistors respectively and a reference potential.
References Cited (Backward Citations)
US3448295A
Cited
US3660827A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-26 | 1981-12-26 | 1982-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-26 | 1985-12-26 | 1986-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-26 | 1989-12-26 | 1990-06-27 | $7700.00 | Window Closed / Lapsed |