Arc-cosine phase modulators

Claim 2

A phase modulator responsive to an input signal and to a carrier signal comprising: first means for developing a signal proportional to the inverse hyperbolic tangent of said input signal; second means, responsive to said first means and to said carrier signal for generating a signal which is proportional to a sum of two signals that are exponentially related to the output signal of said first means and which is amplitude modulated with said carrier signal; and third means for hard limiting the output signal of said second means.

Claim 3

A circuit for generating phase modulated signals responsive to a modulating input signal and to a carrier signal comprising: first means for developing a signal proportional to the inverse hyperbolic tangent of said input signal; second means, responsive to said first means and to said carrier signal, for generating a signal proportional to said carrier signal and to a sum of two signals which are exponentially related to the output signal of said first means; third means for hard limiting the output signal of said second means; and fourth means for filtering the output signal of said third means.

Claim 4

A circuit for generating phase modulated signals responsive to a modulating input signal and to a carrier signal comprising: first means for developing a signal proportional to the inverse hyperbolic tangent of said input signal; second means, responsive to said first means and to said carrier signal, for generating a signal proportional to said carrier signal and to a sum of two signals which are exponentially related to the output signal of said first means; third means for hard limiting the output signal of said second means; and fourth means for filtering the output signal of said third means.

Claim 5

The circuit of claim 2 wherein said second means develops the signal B(e x +je -x ) 2 , where x is the output signal of said first means and B is said carrier signal.

Claim 6

The apparatus of claim 3 wherein said filter means is a bandpass filter generally centered at the frequency of said carrier signal.

Claim 7

The apparatus of claim 2 wherein said second means develops the signal B(e x +je -x ) where x is the output signal of said first means and B is said carrier signal.

Claim 8

The circuit of claim 5 wherein said filter is a bandpass filter generally centered about a frequency that is twice the frequency of said carrier.

Claim 9

The circuit of claim 2 wherein said first means approximates the inverse hyperbolic tangent function of said input signal, designated x, realizing the function (1/F)sinh Fx, where F is a preselected constant.

Claim 10

The circuit of claim 2 wherein said second means comprises: a differential amplifier stage developing a first output signal proportional to said carrier signal and to an exponential term related to the output signal of said first means, and a second output signal proportional to said carrier signal and to an exponential term related to the negative of said output signal of said first means; and a quadrature summation stage developing a sum signal of said first output signal of said differential amplifier stage and 90° phase shifted replica of said second output signal of said differential amplifier stage.

Claim 11

A circuit for developing two signals which are phase modulated with respect to a carrier signal with equal but oppositely signed phase angles relating to the arc-cosine of an input signal comprising: an inverse hyperbolic tangent circuit responsive to said input signal for developing a signal proportional to tanh -1 of said input signal; a differential amplifier stage, responsive to the output signal of said inverse hyperbolic tangent circuit and to a carrier signal, for generating a first output signal proportional to said carrier signal and to an exponential term related to the output signal of said inverse hyperbolic tangent circuit, and for generating a second output signal proportional to said carrier signal and to an exponential term related to the negative of the output signal of said inverse hyperbolic tangent circuit; first quadrature summation stage for developing a sum signal of said first output signal of said differential stage and a 90° phase shifted replica of said second output of said differential amplifier stage; a second quadrature summation stage developing a sum signal of said second output signal of said differential amplifier stage and a 90° phase shifted replica of said first output signal of said differential amplifier stage; means for hard limiting the output signals of said first and second quadrature summation stages; and means for filtering the output signals of said means for hard limiting.

Claim 12

A circuit for developing two signals which are phase modulated with respect to a carrier signal with equal but oppositely signed phase angles relating to the arc-cosine of an input signal comprising: an inverse hyperbolic tangent circuit responsive to said input signal for developing a signal proportional to tanh -1 of said input signal; a differential amplifier stage, responsive to the output signal of said inverse hyperbolic tangent circuit and to a carrier signal, for generating a first output signal proportional to said carrier signal and to an exponential term related to the output signal of said inverse hyperbolic tangent circuit, and for generating a second output signal proportional to said carrier signal and to an exponential term related to the negative of the output signal of said inverse hyperbolic tangent circuit; first quadrature summation stage for developing a sum signal of said first output signal of said differential stage and a 90° phase shifted replica of said second output of said differential amplifier stage; a second quadrature summation stage developing a sum signal of said second output signal of said differential amplifier stage and a 90° phase shifted replica of said first output signal of said differential amplifier stage; means for hard limiting the output signals of said first and second quadrature summation stages; and means for filtering the output signals of said means for hard limiting.

Claim 13

The circuit of claim 9 further including means, interposed between said first and second quadrature summation stages and said means for hard limiting, for squaring the output signals of said first and second quadrature summation stages.