US4093851A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Means and methods for detecting the possibility of a failure occurring in the operation of a digital circuit
Assignee: Unisys Corp
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Filing: 1976-12-27
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Granted: 1978-06-06
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Expires: 1996-12-27
Abstract
Abstract Improved means and methods for detecting the possibility of a failure occurring in the operation of a digital circuit when operating in a normal manner in a data processing system without any previous or present failure having occurred. In a particular preferred embodiment, the potential possibility of a failure occurring in a clocked digital circuit is detected by determining whether an input signal applied to the digital circuit is stable for a predetermined minimum time period relative to the clock.
Inventors
- 👤 Ronald Adam Paulinski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:04
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
142 words
Potential failure detecting means for detecting the possibility of a potential failure occurring in a digital circuit while the circuit is operating in a data processing system in a normal manner without failure, said potential failure detecting means comprising: means coupled to a communication line provided between said data processing system and said digital circuit for deriving a test signal indicative of a signal communicated between said digital circuit and said system during actual operation of said circuit in said system; criteria establishing means for generating a potential failure criteria signal indicative of predetermined criteria for said test signal, said criteria signal having a predetermined timing characteristic; comparing means for comparing time relationships between said test signal and said criteria signal; and indicating means responsive to said comparing means for providing an indication of whether said test signal meets said predetermined criteria.
Claim 2
Dependent Claim
142 words
Potential failure detecting means for detecting the possibility of a potential failure occurring in a digital circuit while the circuit is operating in a data processing system in a normal manner without failure, said potential failure detecting means comprising: means coupled to a communication line provided between said data processing system and said digital circuit for deriving a test signal indicative of a signal communicated between said digital circuit and said system during actual operation of said circuit in said system; criteria establishing means for generating a potential failure criteria signal indicative of predetermined criteria for said test signal, said criteria signal having a predetermined timing characteristic; comparing means for comparing time relationships between said test signal and said criteria signal; and indicating means responsive to said comparing means for providing an indication of whether said test signal meets said predetermined criteria.
Claim 3
Dependent Claim
36 words
The invention in accordance with claim 1 wherein said criteria signal establishes a predetermined time period, and wherein said comparison means includes means for determining whether said test signal is stable over said predetermined time period.
Claim 4
Dependent Claim
37 words
The invention in accordance with claim 2, wherein said communication line is an input line, and wherein said comparison means is operative to determine whether a transition occurs in said test signal during said predetermined time period.
Claim 5
Dependent Claim
40 words
The invention in accordance with claim 2, wherein said digital circuit operates in response to an applied clock, and wherein said predetermined time period of said criteria signal is chosen to have a predetermined timing relationship relative to said clock.
Claim 6
Dependent Claim
75 words
The invention in accordance with claim 4, wherein said predetermined timing relationship between said clock and said predetermined time period of said criteria signal is chosen in conjunction with said comparing means so that said comparing means provides an output signal to said indicating means which indicates whether said test signal is stable from a predetermined time prior to operation of said digital circuit in response to said clock to a predetermined time subsequent thereto.
Claim 7
Dependent Claim
44 words
The invention in accordance with claim 3, wherein said comparison means includes means for delaying said test signal, and means responsive to the delayed and undelayed test signal for producing a signal in response to the occurrence of a transition in said test signal.
Claim 8
Independent Claim
133 words
A method of detecting the possibility of a potential failure occurring in a digital circuit while the circuit is operating in a data processing system in a normal manner without failure, said method comprising the steps of: deriving a test signal indicative of a signal communicated between said digital circuit and said system during actual operation of said circuit in said system; generating a potential failure criteria signal indicative of predetermined criteria which must be met by said test signal in order to obtain reliable operation of said circuit, said criteria signal having a predetermined timing characteristic; comparing time relationships between said test signal and said criteria signal to determine whether said predetermined criteria are satisfied; and indicating in response to the step of comparing whether said test signal meets said predetermined criteria.
Claim 9
Independent Claim
133 words
A method of detecting the possibility of a potential failure occurring in a digital circuit while the circuit is operating in a data processing system in a normal manner without failure, said method comprising the steps of: deriving a test signal indicative of a signal communicated between said digital circuit and said system during actual operation of said circuit in said system; generating a potential failure criteria signal indicative of predetermined criteria which must be met by said test signal in order to obtain reliable operation of said circuit, said criteria signal having a predetermined timing characteristic; comparing time relationships between said test signal and said criteria signal to determine whether said predetermined criteria are satisfied; and indicating in response to the step of comparing whether said test signal meets said predetermined criteria.
Claim 10
Dependent Claim
40 words
The invention in accordance with claim 7 wherein the step of generating provides a criteria signal indicative of a predetermined time perod, and wherein the step of comparing determines whether said test signal is stable over said predetermined time period.
Claim 11
Dependent Claim
26 words
The invention in accordance with claim 7, wherein the step of comparing determines whether a transition occurs in said test signal during said predetermined time period.
Claim 12
Dependent Claim
48 words
The invention in accordance with claim 7, wherein said digital circuit operates in response to an applied clock, and wherein the step of generating provides said predetermined time period of said criteria signal in a manner so that it has a predetermined timing relationship relative to said clock.
Claim 13
Dependent Claim
65 words
The invention in accordance with claim 10, wherein said predetermined timing relationship between said clock and said predetermined time period of said criteria signal is chosen so that the steps of comparing and indicating cooperate to indicate whether said test signal is stable from a predetermined time prior to operation of said digital circuit in response to said clock to a predetermined time subsequent thereto.
References Cited (Backward Citations)
US3386079A
Cited
US3396369A
Cited
US3548178A
Cited
US3548177A
Cited
US3548176A
Cited
US4034340A
Cited
US4032884A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-05 | 1981-12-05 | 1982-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-05 | 1985-12-05 | 1986-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-05 | 1989-12-05 | 1990-06-06 | $7700.00 | Window Closed / Lapsed |