Frequency multiplier and level detector

Abstract

Abstract A frequency multiplier and level detector circuit is disclosed and includes a plurality of switching devices with the first one of said switching devices and the remaining one or ones thereof being interconnected in successive stages, and being switchable between first and second states in response to predetermined values of an input pulse. The switching devices each have a thresholding network associated therewith, and the switching devices are interconnected so that when the second or any subsequent ones of the switching devices is switched into the first state in response to the input pulse, it causes the preceding stage of the switching device to switch to the second state, thereby producing a number of output pulses at the first stage of the switching devices, which number of output pulses is dependent upon the number of the switching devices which have been switched into the first state. BACKGROUND OF THE INVENTION This invention relates to a frequency multiplier and level detector circuit. The circuit of this invention has many applications in EDP equipment, the automotive industry, digital communications, test instrumentation, and situations requiring an analog to digital converter. For example, when the circuit of this invention is used as a level detector circuit, it can be used as a voltage level discriminator in a test instrument, such as a multimeter, to automatically select the proper voltage range for the instrument when testing an unknown voltage. In general, this circuit can be used to discriminate analog voltage levels and to convert these levels to digital pulse information which is useful for digital manipulation, as for example in EDP majority logic circuitry. When the circuit of this invention is used as a frequency multiplier, the circuit will multiply input pulses by a factor determined by the number of stages in the circuit and/or the input pulse voltage amplitude. For example, if the number of stages in the circuit is N, there will be N pulses generated at the output of the circuit for each input pulse. In EDP and communications type networks, this circuit could perform arithmetic in conjunction with currently available digital counters or other circuit logic. Some prior art disclosures which relate to frequency multiplier circuits and circuits having plural amplitude responsive stages are shown in the following U.S. patents and publications: U.S. Pat. No. 2,486,390 U.S. Pat. No. 3,097,309 U.S. Pat. No. 3,535,549 U.S. Pat. No. 3,539,831 and U.S. Pat. No. 3,743,946; and Beisner: Analog to Digital Conversion Device, IBM Technical Disclosure Bulletin, Volume 7, No. 11, April 1965, pgs. 1054-1055. None of these disclosures shows a frequency multiplier and level detector circuit which is amplitude responsive and in which the output from the circuit alternately takes on one of two values as the input to the circuit increases monotonically. SUMMARY OF THE INVENTION This invention relates to a circuit which includes a plurality of circuit means or switching means which are switchable between first and second states, with the first one and the remaining one or ones of said plurality being interconnected in successive stages and with means for supplying an input pulse to each of the switching means to enable each of the switching means to switch to the first state (or to assume the first state) in response to predetermined values of the input pulse. There are also means interconnecting the switching means so that when the second or any subsequent one of the switching means in the successive stages is switched to the first state in response to the input pulse, the second or any subsequent one of the switching means causes the preceding switching means to switch to the second state, thereby producing a number of pulses at the first one of the switching means. The number of output pulses is dependent upon the number of the switching means which have been switched into the first state in response to the input pulse.

Inventors

• 👤 Donald K. Lauffer

Bibliographic Details