Self-adjusting compatibility circuit for digital to analog converter

Claim 2

A logic compatibility circuit for interfacing a digital to analog converter having positive and negative voltage supplies with logic input signals corresponding to first and second logic systems, such that appropriate threshold switching signals compatible with each logic system are automatically presented to the converter when a logic control signal from either system is applied to the circuit, said first logic system being characterized by a logic control signal within a first voltage range and by a switching threshold which differs from the logic control signals by a fixed increment, said second logic system being characterized by a logic control signal within a second range which is higher in voltage than said first range, and by a switching threshold equal to a substantially fixed proportion of the positive supply voltage, said circuit comprising: a positive supply voltage bus, a negative supply voltage bus, a logic control input terminal, an output terminal adapted to provide a threshold switching signal to a digital to analog converter, an impedance circuit connected between said positive bus and said output terminal, the voltage at said output terminal being determined by the current through said impedance circuit, a voltage incrementing circuit connected to said output terminal to draw current through said impedance circuit and thereby establish an output terminal voltage, said incrementing circuit being connected to said input terminal for biasing such that the current drawn thereby establishes an output signal which differs from the input voltage by a substantially fixed incremental amount, said incrementing circuit including a threshold means adapted to terminate said current drawn when the logic control signal at said input terminal exceeds a predetermined threshold corresponding to the upper limit of said first range, an output circuit connected to said output terminal to draw a current through said impedance circuit, the magnitude of which is directly proportional to said positive bus voltage and sufficient to satisfy the input-output voltage relationship of said second logic system, and a bypass circuit adapted to divert the current drawn by said output circuit away from said impedance circuit when the logic control signal at said input terminal is less than said first range, thereby causing the output terminal voltage to be determined by said voltage incrementing circuit when the logic control voltage at said input terminal is within said first range, and by said output circuit when the logic control voltage is within said second range.

Claim 3

The logic compatibility circuit of claim 1, said output circuit comprising a current mirror having a reference circuit connected between said positive and negative buses to provide a reference current the magnitude of which varies in substantially direct proportion to the voltage differential between said buses, and a mirror circuit connected to said output terminal.

Claim 4

The logic compatibility circuit of claim 2, said bypass circuit comprising a current source connected through a switch means to supply the current drawn by said mirror circuit, said switch means being connected to terminate said current supply in response to operation of said first threshold means.

Claim 5

The logic compatibility of claim 2, further comprising an offset current source connected to supply current to said mirror circuit sufficient to offset the current contribution of said negative voltage supply bus, thus enabling the current drawn through said impedance circuit by said mirror, and thereby the output terminal voltage, to vary in direct proportion to the positive supply voltage.

Claim 6

The logic compatibility circuit of claim 2, and further including additional circuitry for interfacing the converter with a third logic system characterized by an open circuit logic control signal and a substantially constant switching threshold for a given positive supply voltage level, said additional circuitry comprising: a current source means connected to apply a current to said input terminal to elevate the voltage level thereof, current diversion means connected to said input terminal to divert the current applied thereto from said source when the input terminal voltage exceeds a predetermined level between said first and second voltage ranges, thereby maintaining the open circuit input terminal voltage substantially at said predetermined level, and means for altering the mirror ratio of said current mirror from a ratio, for an input logic control voltage within said second range, at which the current drawn through said impedance circuit produces an output terminal voltage compatible with said second logic system, to a ratio for an input logic control voltage at said predetermined level, at which the output terminal voltage is compatible with said third logic system.

Claim 7

The logic compatibility circuit of claim 5, said current mirror including a double emitter mirror transistor, the mirror ratio being determined by the pattern of conductive emitters, said ratio altering means comprising a differential switch and controlled by the logic control voltage at said input terminal, and a bias circuit biasing said differential switch to operate when the logic control voltage is substantially equal to the lower limit of said second range, one branch of said switch being connected in circuit with an emitter of said mirror transistor to reverse bias said emitter and thereby establish one mirror ratio when the differential switch is in one state, and to permit forward biasing of said emitter and the establishment of a different mirror ratio when the differential switch is in its other state.

Claim 8

The logic compatibility circuit of claim 6, further comprising an offset current source connected to supply current to said mirror circuit sufficient to offset the current contribution of said negative voltage supply bus, thus enabling the current drawn through said impedance circuit by said mirror, and thereby the output terminal voltage, to vary in direct proportion to the positive supply voltage, said offset current source being connected to said mirror through that branch of said differential switch which is conductive when the logic control input voltage is within said second range.

Claim 9

The logic compatibility circuit of claim 1, adapted for use with a second logic system in which the logic control signal is substantially equal to the positive supply voltage, and the threshold switching voltage is substantially equal to half the logic control voltage.

Claim 10

A logic compatibility circuit for interfacing a digital to analog converter having positive and negative voltage supplies with logic control signals corresponding to first, second, and third logic systems, such that appropriate threshold switching signals compatible with each logic system are automatically presented to the converter when a logic control signal from any of the systems is applied to the circuit, said first logic system being characterized by a logic control signal within a first voltage range and by a switching threshold which differs from the logic control signal by a fixed increment, said second logic system being characterized by a logic control signal within a second voltage range and substantially equal to the positive supply voltage, said second range being at a higher voltage level than said first range, and by a switching threshold equal to a fixed proportion of the positive voltage supply, and said third logic system being characterized by an open circuit logic control signal and by a substantially constant switching threshold for a predetermined positive supply voltage level, said circuit comprising: a positive voltage bus, a negative voltage bus, a logic control input terminal, an output terminal adapted to provide a threshold switching signal to a digital to analog converter, a voltage incrementing circuit connected between said input and output terminals for constraining the voltage at said output terminal to a value which differs from the voltage at said input terminal by a substantially fixed incremental amount, first threshold means adapted to decouple the incrementing circuit connection between said input and output terminals when the logic control signal at said input terminal exceeds a predetermined threshold corresponding to the upper limit of said first range, a reference current circuit connected between said positive and negative buses to provide a reference current the magnitude of which varies in substantially direct proportion to the voltage differential between said positive and negative buses, a current mirror circuit adapted to proportionately mirror said reference current, said mirror circuit comprising: a mirror element connected in circuit with said negative voltage bus to proportionately mirror the current in said reference current circuit, a first circuit portion connected between said positive voltage bus and said mirror element, said output terminal being connected to said first circuit portion so that the output voltage level is determined by the combination of the positive bus voltage and the current through said portion, and a second circuit portion comprising an offset current source connected to provide an offset current to said mirror element of a magnitude sufficient to compensate for the contribution to the current through the first portion of said negative voltage bus, thereby enabling the current through the first portion and accordingly the output voltage level to vary in substantially direct proportion to the positive bus voltage when the logic control signal is within said second voltage range, second threshold means adapted to alter the mirror ratio, at a predetermined input terminal voltage corresponding to the lower limit of said second voltage range, from a ratio below said second threshold level at which the output voltage is at the desired level for said third logic system, to a ratio above said second threshold level at which the output voltage is at the desired level for said second logic system, and circuit means for establishing an input terminal voltage level between said first and second threshold levels during an open circuit logic control input.

Claim 11

A logic compatibility circuit for interfacing a digital to analog converter having positive and negative voltage supplies with logic control signals corresponding to first, second, and third logic systems, such that appropriate threshold switching signals compatible with each logic system are automatically presented to the converter when a logic control signal from any of the systems is applied to the circuit, said first logic system being characterized by a logic control signal within a first voltage range and by a switching threshold which differs from the logic control signal by a fixed increment, said second logic system being characterized by a logic control signal within a second voltage range and substantially equal to the positive supply voltage, said second range being at a higher voltage level than said first range, and by a switching threshold equal to a fixed proportion of the positive voltage supply, and said third logic system being characterized by an open circuit logic control signal and by a substantially constant switching threshold for a predetermined positive supply voltage level, said circuit comprising: a positive voltage bus, a negative voltage bus, a logic control input terminal, an output terminal adapted to provide a threshold switching signal to a digital to analog converter, a voltage incrementing circuit connected between said input and output terminals for constraining the voltage at said output terminal to a value which differs from the voltage at said input terminal by a substantially fixed incremental amount, first threshold means adapted to decouple the incrementing circuit connection between said input and output terminals when the logic control signal at said input terminal exceeds a predetermined threshold corresponding to the upper limit of said first range, a reference current circuit connected between said positive and negative buses to provide a reference current the magnitude of which varies in substantially direct proportion to the voltage differential between said positive and negative buses, a current mirror circuit adapted to proportionately mirror said reference current, said mirror circuit comprising: a mirror element connected in circuit with said negative voltage bus to proportionately mirror the current in said reference current circuit, a first circuit portion connected between said positive voltage bus and said mirror element, said output terminal being connected to said first circuit portion so that the output voltage level is determined by the combination of the positive bus voltage and the current through said portion, and a second circuit portion comprising an offset current source connected to provide an offset current to said mirror element of a magnitude sufficient to compensate for the contribution to the current through the first portion of said negative voltage bus, thereby enabling the current through the first portion and accordingly the output voltage level to vary in substantially direct proportion to the positive bus voltage when the logic control signal is within said second voltage range, second threshold means adapted to alter the mirror ratio, at a predetermined input terminal voltage corresponding to the lower limit of said second voltage range, from a ratio below said second threshold level at which the output voltage is at the desired level for said third logic system, to a ratio above said second threshold level at which the output voltage is at the desired level for said second logic system, and circuit means for establishing an input terminal voltage level between said first and second threshold levels during an open circuit logic control input.

Claim 12

The logic compatibility circuit of claim 9, said second current mirror circuit portion including a switch means connected in circuit with said offset current source and mirror element, said switch means being controlled by the logic control voltage signal at said input terminal to complete a circuit between said offset current source and mirror element when the logic control voltage exceeds a predetermined voltage level corresponding to the lower limit of said second voltage range.

Claim 13

The circuit of claim 10, said switch means comprising a first differential switch, a first branch of said differential switch being connected for biasing by the logic control signal at said input terminal, and a second branch switchingly connected in said second current mirror circuit portion.

Claim 14

The circuit of claim 11, said mirror element including a current actuable means for altering the mirror ratio, said first differential switch branch being connected in circuit with said ratio altering means to provide said second threshold means.

Claim 15

The circuit of claim 12, said mirror element comprising a double emitter transistor, each emitter connected to the negative voltage bus through a respective resistor, the first branch of said differential switch being connected in circuit with the resistor for one emitter to transmit a current thereto sufficient to reverse bias its associated emitter and thereby alter the mirror ratio.

Claim 16

The circuit of claim 11, said first logic system being characterized by a threshold switching voltage at the upper limit of its logic control voltage range which exceeds the threshold switching voltage at the lower limit of the logic control voltage range for said second logic system, wherein the first threshold means comprises a second current source and a second differential switch, one branch of said switch being connected in circuit with said input terminal for biasing by the logic control voltage signal, said second differential switch being connected to route the current from said second source to said current mirror element when the logic control signal is below said first threshold level, thereby decreasing the current in the first portion of the mirror circuit to a level at which the output bias voltage is determined by said voltage incrementing circuit, said second differential switch further being connected to divert the current from said second source away from said current mirror element when the logic control signal is greater than said first threshold level, thereby increasing the current in the first portion of the mirror circuit to a level at which that portion determines the output terminal voltage.

Claim 17

The circuit of claim 14, said voltage incrementing circuit including a diode means connected to conduct current from the output terminal towards the input terminal, said diode means enabling the logic control input voltage to exceed the output terminal voltage when the logic control voltage exceeds said first threshold level.

Claim 18

The circuit of claim 14, said first current mirror branch circuit including a resistor means connected in circuit between said positive voltage bus and said mirror element, said output terminal and voltage incrementing circuit each being connected to said first branch circuit on the mirror element side of said resistor means, whereby the output voltage varies in negative proportion to the current through said first branch circuit for a given positive supply voltage.

Claim 19

The circuit of claim 14, including means to apply a common voltage to one arm of each of said first and second differential switches, the other arms of said switches being connected for control by a logic control signal at said input terminal by circuits which are adapted to present switching voltages to said first and second differential switches which are respectively less and greater than said logic control signal, thereby causing the second differential switch to operate at a lower logic control signal than the first differential switch.

Claim 20

The circuit of claim 9, wherein said means for establishing the input terminal voltage level during an open circuit logic control input comprises a PNP transistor in said voltage incrementing circuit having its bus connected to said input terminal, a current source means connected to supply a current to the base of said transistor to elevate the voltage level thereof, and current diversion means connected to said transistor base to divert the current supplied thereto by said source when the base and input terminal voltages exceed a predetermined level between said first and second voltage ranges.

Claim 21

A logic compatibility circuit for interfacing a digital to analog converter having positive and negative voltage supplies with logic input signals corresponding to first, second, and third logic systems, such that appropriate threshold switching signals compatible with each logic system are automatically presented to the converter when a logic control signal from any of the systems is applied to the circuit, said first logic system being characterized by a logic control signal within a first voltage range and by a switching threshold which differs from the logic control signal by a fixed increment, said second logic system being characterized by a logic control signal within a second voltage range substantially equal to the positive supply voltage, said second range being at a higher voltage level than said first range, and by a switching threshold equal to a fixed proportion of the positive supply voltage, and said third logic system being characterized by an open circuit logic control signal and by a substantially constant switching threshold for a predetermined positive supply voltage level, said circuit comprising: a logic control input terminal, a positive voltage bus, a negative voltage bus, an output terminal adapted to provide threshold switching signal to a digital to analog converter, a current mirror having a reference circuit connected between said positive and negative buses to draw a reference current the magnitude of which is proportional to the voltage differential between said buses, and a mirror circuit connected between said output terminal and the negative bus to draw a current proportional to the reference current, said mirror circuit including a double emitter transistor mirror element, a resistance means connected between said output terminal and said positive bus, an offset current source connected to said mirror circuit to supply the mirror current attributable to said negative bus, whereby the remainder of the mirror current attributable to the positive bus is routed to the mirror through said resistance means, a differential switch having a first branch connected in circuit between said offset current source and said mirror circuit, the second branch of said switch being connected between said offset current source and one emitter of said transistor mirror element to reverse bias said emitter, the mirror ratio being selected to produce a current magnitute through said resistance means which establishes an output terminal voltage satisfying the logic control-threshold switching relationship for the second logic system when both emitters of the transistor element are conductive, and for the third logic system when said one emitter is reverse biased, means biasing said differential switch to render the first branch conductive when the logic control voltage applied to the input terminal is above a level corresponding to the lower limit of said second range, and to render the second branch conductive when the logic control voltage is less than said level, a voltage incrementing circuit connected between said input and output terminals, comprising a grounded collector PNP transistor having its base connected to said input terminal, and a diode means connected to conduct current from said output terminal to the emitter of said transistor, current source means adapted to produce a current sufficient to supply the difference between the mirror current and the current carried by said resistance means when the input logic control signal is within said first range, and a switching circuit connecting said current source means with said mirror transistor, and means biasing said switching circuit to complete said connection when the logic control signal is at a level less than the level corresponding to the upper limit of said first range, and to break said connection when the logic control signal is at a higher voltage level.

Claim 22

A logic compatibility circuit for interfacing a digital to analog converter having positive and negative voltage supplies with logic input signals corresponding to first, second, and third logic systems, such that appropriate threshold switching signals compatible with each logic system are automatically presented to the converter when a logic control signal from any of the systems is applied to the circuit, said first logic system being characterized by a logic control signal within a first voltage range and by a switching threshold which differs from the logic control signal by a fixed increment, said second logic system being characterized by a logic control signal within a second voltage range substantially equal to the positive supply voltage, said second range being at a higher voltage level than said first range, and by a switching threshold equal to a fixed proportion of the positive supply voltage, and said third logic system being characterized by an open circuit logic control signal and by a substantially constant switching threshold for a predetermined positive supply voltage level, said circuit comprising: a logic control input terminal, a positive voltage bus, a negative voltage bus, an output terminal adapted to provide threshold switching signal to a digital to analog converter, a current mirror having a reference circuit connected between said positive and negative buses to draw a reference current the magnitude of which is proportional to the voltage differential between said buses, and a mirror circuit connected between said output terminal and the negative bus to draw a current proportional to the reference current, said mirror circuit including a double emitter transistor mirror element, a resistance means connected between said output terminal and said positive bus, an offset current source connected to said mirror circuit to supply the mirror current attributable to said negative bus, whereby the remainder of the mirror current attributable to the positive bus is routed to the mirror through said resistance means, a differential switch having a first branch connected in circuit between said offset current source and said mirror circuit, the second branch of said switch being connected between said offset current source and one emitter of said transistor mirror element to reverse bias said emitter, the mirror ratio being selected to produce a current magnitute through said resistance means which establishes an output terminal voltage satisfying the logic control-threshold switching relationship for the second logic system when both emitters of the transistor element are conductive, and for the third logic system when said one emitter is reverse biased, means biasing said differential switch to render the first branch conductive when the logic control voltage applied to the input terminal is above a level corresponding to the lower limit of said second range, and to render the second branch conductive when the logic control voltage is less than said level, a voltage incrementing circuit connected between said input and output terminals, comprising a grounded collector PNP transistor having its base connected to said input terminal, and a diode means connected to conduct current from said output terminal to the emitter of said transistor, current source means adapted to produce a current sufficient to supply the difference between the mirror current and the current carried by said resistance means when the input logic control signal is within said first range, and a switching circuit connecting said current source means with said mirror transistor, and means biasing said switching circuit to complete said connection when the logic control signal is at a level less than the level corresponding to the upper limit of said first range, and to break said connection when the logic control signal is at a higher voltage level.

Claim 23

The logic compatibility circuit of claim 19, and further including a current source means connected to the base of said PNP transistor to provide a current thereto sufficient to reverse bias said transistor and open said switching circuit during an open circuit logic control signal, and a current diversion circuit connected to divert said current when the input terminal voltage is at a level between said first and second ranges and thereby prevent said differential switch from changing state.