US4084402A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timing circuit for display sequencing in a digital wristwatch
Assignee: Raytheon Co
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Filing: 1975-05-22
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Granted: 1978-04-18
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Expires: 1995-05-22
Abstract
Abstract A digital timing circuit in a digital watch with a two digit display. When said circuit is activated by a push button, the two display elements first display the hours information, next are blank for a short duration, then display the minutes information, then go blank until the button is pushed again.
Inventors
- 👤 Norman E. Moyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:52
CPC Classifications
G; G04; G04G; G04G9/00; G04G9/08; G04G9/10; G04G9/107
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
657 words
A digital timing circuit in a digital watch with two electro-optical display elements, when said circuit is activated by a manually operable switch, the timing sequence begins and said display elements display a first set of horological information, then said display elements are blank for a short duration, and finally display a second set of horological information and are then blank again, comprising: a clock pulse source; first gate means having first and second input connections and an output connection; said first input of said first gate connected to said clock pulse source; second gate means having first and second input connections and an output connection; said second input of said first gate connected to said output of said second gate; third gate means having first and second input connections and an output connection; fourth gate means having first and second input connections and an output connection; said output of said third gate connected to said first input of said second gate and to said first input of said fourth gate; said output of said fourth gate connected to said input of said third gate; a manually operable switch for activating said digital timing circuitry, said switch connected to said first input to said third gate; fifth gate means having first, second, third, and fourth input connections and an output connection; first flip-flop having first and second input connections and first and second output connections; second flip-flop having first and second input connections and first and second output connections; third flip-flop having first and second input connections and first and second output connections; fourth flip-flop having first and second input connections and first and second output connections; two phase clock generating means having an input connection connected to said output of said first gate means and having a first output connected to said first input of said first flip-flop and a second output connected to said second input of said first flip-flop; said first output of said first flip-flop connected to said first input of said second flip-flop, to said second input to said second gate and to said first input to said fifth gate; said second output of said first flip-flop connected to said second input of said second flip-flop; sixth gate means having first and second input connections and an output connection; said first output of said second flip-flop connected to said first input of said third flip-flop and to said first input of said sixth gate; said second output of said second flip-flop connected to said second input of said third flip-flop, and to said second input of said fifth gate; said second output from said third flip-flop connected to said third input to said fifth gate and to said second input of said fourth gate for forcing said flip-flop into a known state; said first output of said third flip-flop connected to said first input of said fourth flip-flop; said second output of said third flip-flop connected to said second input of said fourth flip-flop; said first output of said fourth flip-flop connected to said second input of said sixth gate; said second output of said fourth flip-flop connected to said fourth input of said fifth gate; first and second electro-optical display elements which display the digits of first and second sets of horological information; said output of said sixth gate being connected to said first electro-optical display elements; said second output of said third flip-flop being connected to said second electro-optical display elements; said second set of horological information is displayed on said electro-optical display elements when said output of said sixth gate is at a logical binary high level and said second output of said third flip-flop is at a logical binary low level; and said first set of horological information is displayed on said electro optical display elements when said outputs of said sixth gate and said second output of said third flip-flop are at a logical binary high level.
Claim 2
Dependent Claim
657 words
A digital timing circuit in a digital watch with two electro-optical display elements, when said circuit is activated by a manually operable switch, the timing sequence begins and said display elements display a first set of horological information, then said display elements are blank for a short duration, and finally display a second set of horological information and are then blank again, comprising: a clock pulse source; first gate means having first and second input connections and an output connection; said first input of said first gate connected to said clock pulse source; second gate means having first and second input connections and an output connection; said second input of said first gate connected to said output of said second gate; third gate means having first and second input connections and an output connection; fourth gate means having first and second input connections and an output connection; said output of said third gate connected to said first input of said second gate and to said first input of said fourth gate; said output of said fourth gate connected to said input of said third gate; a manually operable switch for activating said digital timing circuitry, said switch connected to said first input to said third gate; fifth gate means having first, second, third, and fourth input connections and an output connection; first flip-flop having first and second input connections and first and second output connections; second flip-flop having first and second input connections and first and second output connections; third flip-flop having first and second input connections and first and second output connections; fourth flip-flop having first and second input connections and first and second output connections; two phase clock generating means having an input connection connected to said output of said first gate means and having a first output connected to said first input of said first flip-flop and a second output connected to said second input of said first flip-flop; said first output of said first flip-flop connected to said first input of said second flip-flop, to said second input to said second gate and to said first input to said fifth gate; said second output of said first flip-flop connected to said second input of said second flip-flop; sixth gate means having first and second input connections and an output connection; said first output of said second flip-flop connected to said first input of said third flip-flop and to said first input of said sixth gate; said second output of said second flip-flop connected to said second input of said third flip-flop, and to said second input of said fifth gate; said second output from said third flip-flop connected to said third input to said fifth gate and to said second input of said fourth gate for forcing said flip-flop into a known state; said first output of said third flip-flop connected to said first input of said fourth flip-flop; said second output of said third flip-flop connected to said second input of said fourth flip-flop; said first output of said fourth flip-flop connected to said second input of said sixth gate; said second output of said fourth flip-flop connected to said fourth input of said fifth gate; first and second electro-optical display elements which display the digits of first and second sets of horological information; said output of said sixth gate being connected to said first electro-optical display elements; said second output of said third flip-flop being connected to said second electro-optical display elements; said second set of horological information is displayed on said electro-optical display elements when said output of said sixth gate is at a logical binary high level and said second output of said third flip-flop is at a logical binary low level; and said first set of horological information is displayed on said electro optical display elements when said outputs of said sixth gate and said second output of said third flip-flop are at a logical binary high level.
Claim 3
Dependent Claim
17 words
The digital timing circuit as recited in claim 1, wherein said second gate is an AND gate.
Claim 4
Dependent Claim
21 words
The digital timing circuit as recited in claim 1, wherein said first, third, fourth, fifth, and sixth gates are NOR gates.
Claim 5
Dependent Claim
532 words
A digital timing circuit in a digital watch with two electro-optical display elements, when said circuit is activated by a manually operable switch the timing sequency begins and said display elements display a first set of horological information, then said display elements are blank for a short duration, and finally display a second set of horological information and are then blank again, comprising; a clock pulse source; first gate means having first and second input connections and an output connection; said first input of said first gate connected to said clock pulse source; second gate means having first and second input connections and an output connection; said second input of said first gate connected to said first input to said second gate; third gate means having first, second and third input connections and an output connection; fourth gate means having first and second input connections and an output connection; said output of said third gate connected to said first input of said second gate and to said second input of said first gate; a manually operable switch for activating said digital timing circuitry, said switch connected to said second input to said second gate; first flip-flop having first and second input connections and first and second output connections; second flip-flop having first and second input connections and first and second output connections; third flip-flop having first and second input connections and first and second output connections; fourth flip-flop having first and second input connections and first and second output connections; two phase clock generating means having an input connection connected to said output of said first gate means and having a first output connected to said first input of said first flip-flop and a second output connected to said second input of said first flip-flop; said first output of said first flip-flop connected to said first input of said second flip-flop; said second output of said first flip-flop connected to said second input of said second flip-flop; said second output of said second flip-flop connected to said first input of said third gate and to said second input of said fourth gate; said second output of said third flip-flop connected to said second input of said fourth flip-flop and to said second input to said third gate; said first output of said fourth flip-flop connected to said first input of said fourth gate; said second output of said fourth flip-flop connected to said third input of said third gate; first and second electro-optical display elements which display the digits of first and second sets of horological information; said output of said sixth gate being connected to said first electro-optical display element; said second output of said third flip-flop being connected and said second electro-optical display element; said second set of horological information is displayed on said electro-optical display when said output of said fourth gate is at a logical binary high level and said second output of said third flip-flop is a a logical binary low level; and said first set of horological information is displayed on said electro-optical display when said outputs of said fourth gate and said second output of said third flip-flop are at a logical binary high level.
Claim 6
Dependent Claim
532 words
A digital timing circuit in a digital watch with two electro-optical display elements, when said circuit is activated by a manually operable switch the timing sequency begins and said display elements display a first set of horological information, then said display elements are blank for a short duration, and finally display a second set of horological information and are then blank again, comprising; a clock pulse source; first gate means having first and second input connections and an output connection; said first input of said first gate connected to said clock pulse source; second gate means having first and second input connections and an output connection; said second input of said first gate connected to said first input to said second gate; third gate means having first, second and third input connections and an output connection; fourth gate means having first and second input connections and an output connection; said output of said third gate connected to said first input of said second gate and to said second input of said first gate; a manually operable switch for activating said digital timing circuitry, said switch connected to said second input to said second gate; first flip-flop having first and second input connections and first and second output connections; second flip-flop having first and second input connections and first and second output connections; third flip-flop having first and second input connections and first and second output connections; fourth flip-flop having first and second input connections and first and second output connections; two phase clock generating means having an input connection connected to said output of said first gate means and having a first output connected to said first input of said first flip-flop and a second output connected to said second input of said first flip-flop; said first output of said first flip-flop connected to said first input of said second flip-flop; said second output of said first flip-flop connected to said second input of said second flip-flop; said second output of said second flip-flop connected to said first input of said third gate and to said second input of said fourth gate; said second output of said third flip-flop connected to said second input of said fourth flip-flop and to said second input to said third gate; said first output of said fourth flip-flop connected to said first input of said fourth gate; said second output of said fourth flip-flop connected to said third input of said third gate; first and second electro-optical display elements which display the digits of first and second sets of horological information; said output of said sixth gate being connected to said first electro-optical display element; said second output of said third flip-flop being connected and said second electro-optical display element; said second set of horological information is displayed on said electro-optical display when said output of said fourth gate is at a logical binary high level and said second output of said third flip-flop is a a logical binary low level; and said first set of horological information is displayed on said electro-optical display when said outputs of said fourth gate and said second output of said third flip-flop are at a logical binary high level.
Claim 7
Dependent Claim
17 words
The digital timing circuit as recited in claim 4, wherein said second gate is an AND gate.
Claim 8
Dependent Claim
19 words
The digital timing circuit as recited in claim 4, wherein said first, third, and fourth gates are NOR gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-17 | 1981-10-17 | 1982-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-17 | 1985-10-17 | 1986-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-17 | 1989-10-17 | 1990-04-18 | $7700.00 | Window Closed / Lapsed |