US4084258A
Expired / Lapsed
US
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Apparatus for performing multiple operations in a shift register memory
Assignee: International Business Machines Corp
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Filing: 1974-04-22
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Granted: 1978-04-11
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Expires: 1994-04-22
Abstract
Abstract An apparatus for performing multiple operations during a memory revolution in an electronic dynamic shift register. The memory is initially arranged by the input of control codes such as record, operation, separator, and hold flags. The separator flag defines a normal section and an alternate section, and the operation and hold flags define the position of the next character to be addressed in each of the sections. The record flag is the operating point for an output operation in the normal section. When one of the sections is addressed and it does not contain the operation flag, the hold and operation flags are exchanged in order that the operation flag is in the section addressed. With the operation flag in the normal section, an input zone is defined by the separator flag in the alternate section, and a revision zone is defined from the record flag to the separator flag in the normal section. When the operation flag is in the alternate section, the input zone begins with the first dummy code following the operation flag, and the revision zone is from the separator flag to the first dummy code. An output zone is defined in the normal section by inserting a page end code and extends from the record flag through the page end code. When the page end code is inserted, the revision zone is redefined from the page end code to the separator flag. This arrangement of memory allows for multiple operations such as input, output, and revision to be performed during any one memory revolution. Upon decode of the control codes defining the sections and zones, initiated operations are performed and controlled.
Inventors
- 👤 Robert Glenn Bluethman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:16
CPC Classifications
B; B41; B41J; B41J5/00; B41J5/30; B41J5/44; G; G06; G06F; G06F40/00; G06F40/10; G06F40/12; G06F40/123; G06F40/166
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
458 words
An input/output system for arranging control codes to define sections and zones in a recirculating electronic shift register memory, and performing multiple operations after said control codes have been arranged, said system including a bulk store, a keyboard, and a printer and comprising in combination: (I) writing means connected to said memory and including a) a buss along which data codes are applied to and from said keyboard, printer, and bulk store, b) register and gating means for inserting and writing data and control codes into, deleting data and control codes from, and reading data and control codes out of, said memory, and c) a plurality of control lines along which logical signals are applied when data and control codes are to be gated through said gating means; (II) decode means connected to said memory for decoding control codes in said memory upon each revolution thereof in said memory; and (III) control means including logical circuitry connected to said decode means and said control lines of said writing means for applying logical signals to said control lines to cause said writing means to initially randomly write a first control code into said memory for defining a normal section, an alternate section, and an expandable input zone in said alternate section, and to write a second control code into said memory adjacent said first control code for defining an expandable revision zone in said normal section; said control means further including means for applying logical signals to said control lines dependent upon the particular operations to be performed and dependent upon said decoding of said control codes by said decode means; said control means further including: (1) means for performing an input operation wherein a number of data codes and a new first control code are written, by said writing means, into said input zone and over at least said first control code in said memory after said first control code has been decoded by said decode means; wherein said zones and sections are redefined through writing said new first control code into said memory following the last of said data codes written into said memory; (2) means for performing a revision operation wherein a number of data codes are inserted and written into, and deleted from, said revision zone, by said writing means, after said second control code has been decoded by said decode means; and (3) means for performing an output operation wherein data codes are read out of said revision zone by said writing means after said second control code has been decoded by said decode means; said control means further including means for performing at least two of said input, output, and revision operations during a revolution of said first control code in said memory.
Claim 2
Dependent Claim
458 words
An input/output system for arranging control codes to define sections and zones in a recirculating electronic shift register memory, and performing multiple operations after said control codes have been arranged, said system including a bulk store, a keyboard, and a printer and comprising in combination: (I) writing means connected to said memory and including a) a buss along which data codes are applied to and from said keyboard, printer, and bulk store, b) register and gating means for inserting and writing data and control codes into, deleting data and control codes from, and reading data and control codes out of, said memory, and c) a plurality of control lines along which logical signals are applied when data and control codes are to be gated through said gating means; (II) decode means connected to said memory for decoding control codes in said memory upon each revolution thereof in said memory; and (III) control means including logical circuitry connected to said decode means and said control lines of said writing means for applying logical signals to said control lines to cause said writing means to initially randomly write a first control code into said memory for defining a normal section, an alternate section, and an expandable input zone in said alternate section, and to write a second control code into said memory adjacent said first control code for defining an expandable revision zone in said normal section; said control means further including means for applying logical signals to said control lines dependent upon the particular operations to be performed and dependent upon said decoding of said control codes by said decode means; said control means further including: (1) means for performing an input operation wherein a number of data codes and a new first control code are written, by said writing means, into said input zone and over at least said first control code in said memory after said first control code has been decoded by said decode means; wherein said zones and sections are redefined through writing said new first control code into said memory following the last of said data codes written into said memory; (2) means for performing a revision operation wherein a number of data codes are inserted and written into, and deleted from, said revision zone, by said writing means, after said second control code has been decoded by said decode means; and (3) means for performing an output operation wherein data codes are read out of said revision zone by said writing means after said second control code has been decoded by said decode means; said control means further including means for performing at least two of said input, output, and revision operations during a revolution of said first control code in said memory.
Claim 3
Dependent Claim
48 words
A system according to claim 1 wherein said control means includes means for defining an output zone in said normal section through causing said writing means to insert a third control code into said normal section after said second control code has been decoded by said decode means.
Claim 4
Dependent Claim
48 words
A system according to claim 2 wherein said control means includes means for defining an operating point in said normal section through causing said writing means to insert a fourth control code into said normal section after said second control code has been decoded by said decode means.
Claim 5
Dependent Claim
48 words
A system according to claim 3 wherein said control means includes means for defining a holding point in said alternate section through causing said writing means to insert a fifth control code into said alternate section after said first control code has been decoded by said decode means.
Claim 6
Dependent Claim
30 words
A system according to claim 4 wherein said control means includes means for interrupting said system in order that only one of said operations can be performed during said revolution.
Claim 7
Dependent Claim
464 words
In an input/output system having a recirculating electronic shift register memory for storing data and control codes; a keyboard; a printer; a bulk store; writing means connected to said memory and including a) a buss along which said data codes are applied to and from said keyboard, printer, and bulk store, b) register and gating means for inserting and writing data and control codes into, deleting data and control codes from, and reading data and control codes out of, said memory, and c) a plurality of control lines along which logical signals are applied when said data and control codes are to be gated through said gating means; decode means connected to said memory for decoding control codes in said memory upon each revolution thereof in said memory; and control means including logical circuitry connected to said decode means and said control lines of said writing means for applying logical signals to said control lines and causing said writing means to initially randomly write a first control code into said memory for defining a normal section, an alternate section, and an expandable input zone in said alternate section; the improvement comprising: (A) means included in said control means for applying logical signals to said control lines to cause said writing means to write a second control code into said memory adjacent said first control code for defining an expandable revision zone in said normal section; and (B) means included in said control means for performing multiple operations by applying logical signals to said control lines dependent upon said decoding of said control codes by said decode means and the particular operations to be performed; said means included in said control means including: (1) means for performing an input operation wherein a number of data codes are written, by said writing means, into said input zone and over said first control code and following codes in said memory after said first control code has been decoded by said decode means; and wherein said zones and sections are redefined through writing a new first control code into said memory following the last of said data codes written into said memory; (2) means for performing a revision operation wherein a number of data codes are inserted into, written into, or deleted from, said revision zone, by said writing means, after said second control code has been decoded by said decode means; and (3) means for performing an output operation wherein a number of data codes are read out of said revision zone by said writing means after said second control code has been decoded by said decode means; said control means further including means for performing at least two of said input, output, and revision operations during a revolution of said first control code in said memory.
Claim 8
Dependent Claim
464 words
In an input/output system having a recirculating electronic shift register memory for storing data and control codes; a keyboard; a printer; a bulk store; writing means connected to said memory and including a) a buss along which said data codes are applied to and from said keyboard, printer, and bulk store, b) register and gating means for inserting and writing data and control codes into, deleting data and control codes from, and reading data and control codes out of, said memory, and c) a plurality of control lines along which logical signals are applied when said data and control codes are to be gated through said gating means; decode means connected to said memory for decoding control codes in said memory upon each revolution thereof in said memory; and control means including logical circuitry connected to said decode means and said control lines of said writing means for applying logical signals to said control lines and causing said writing means to initially randomly write a first control code into said memory for defining a normal section, an alternate section, and an expandable input zone in said alternate section; the improvement comprising: (A) means included in said control means for applying logical signals to said control lines to cause said writing means to write a second control code into said memory adjacent said first control code for defining an expandable revision zone in said normal section; and (B) means included in said control means for performing multiple operations by applying logical signals to said control lines dependent upon said decoding of said control codes by said decode means and the particular operations to be performed; said means included in said control means including: (1) means for performing an input operation wherein a number of data codes are written, by said writing means, into said input zone and over said first control code and following codes in said memory after said first control code has been decoded by said decode means; and wherein said zones and sections are redefined through writing a new first control code into said memory following the last of said data codes written into said memory; (2) means for performing a revision operation wherein a number of data codes are inserted into, written into, or deleted from, said revision zone, by said writing means, after said second control code has been decoded by said decode means; and (3) means for performing an output operation wherein a number of data codes are read out of said revision zone by said writing means after said second control code has been decoded by said decode means; said control means further including means for performing at least two of said input, output, and revision operations during a revolution of said first control code in said memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-10 | 1981-10-10 | 1982-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-10 | 1985-10-10 | 1986-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-10 | 1989-10-10 | 1990-04-11 | $7700.00 | Window Closed / Lapsed |