High speed monolithic a/d converter utilizing strobe comparator

Claim 1

An analog-to-digital converter of the type using a successive approximation algorithm to quantize an analog input signal comprising: clock means providing a first clock signal characterized by a first frequency and a second clock signal characterized by a second frequency that is greater than said first frequency; shift register means having a plurality of register terminals and being responsive to said first clock signal and operative to sequentially shift a portion of said first clock signal through said register such that said portion of said first clock signal is sequentially applied to said register terminals at said second frequency; latch means comprised of current-mode differential logic that is required to be driven by a binary digital signal having a relatively high voltage, said latch means being responsive to the signal applied on said register terminals and said binary digital signal and operative to store n bits of information regarding the state of said binary digital signal, where n is an integer, to develop n sequencing signals starting with the most significant bit and ending with the least significant bit and further to produce a binary output signal corresponding to said n bits of stored information when said shift register has been sequenced through said plurality of register terminals, said binary output signal being representative of the magnitude of the analog input signal; digital-to-analog converter means responsive to said sequencing signals and operative to sequentially and cyclically provide n reference signals, each being representative of a predetermined voltage in accordance with the binary weighted value of the sequencing signals; and comparator means including a first input terminal for receiving the analog input signal, a second input terminal for sequentially receiving each said reference signal, a control terminal for receiving said second clock signal and an output terminal and being switchable between a first and a second electrical configuration in response to said second clock signal, said first configuration having a relatively low amplification factor and serving to develop an intermediate signal when the magnitude of said reference signal exceeds that of said analog input signal, said second configuration having a relatively large amplification factor and including positive feedback, said second configuration being responsive to said intermediate signal and operative to amplify said intermediate signal so as to provide said binary digital signal on said output terminal, said positive feedback serving to latch said binary digital signal independent of the signals applied to said first and second input terminals, thereby rendering said second configuration insensitive to said analog input signal and said reference signal, said binary digital signal serving to drive said latch means, said latch means serving to store said information regarding the state of said binary digital signal and to produce said binary output signal representative of the magnitude of said analog input voltage.