US4081792A
Expired / Lapsed
US
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Monolithically integrated semiconductor circuit arrangement
Assignee: Licentia Patent Verwaltungs GmbH
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Filing: 1976-03-26
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Granted: 1978-03-28
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Expires: 1996-03-26
Abstract
Abstract A monolithically integrated semiconductor matrix circuit arrangement comprising switching elements which are connected in pairs at one terminal. This common terminal of the pair of switching elements is connected to an input (or output) circuit path and other terminal of each switching element is connected individually to an output (or input) circuit path respectively.
Inventors
- 👤 Hans Schussler
- 👤 Hans-Jurgen Wulf
- 👤 Bernhard Rall
- 👤 Helmut Knapp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:14
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/52; H04Q3/521
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
157 words
In a monolithically integrated semiconductor circuit arrangement, particularly for switching matrices of tele-communications switching systems, including a plurality of semiconductor switching elements arranged in a matrix, a plurality of intersecting input and output circuit paths which are arranged in rows and columns and which may be selectively connected together by means of said switching elements, control or triggering means for switching on or blocking said switching elements to selectively connect said input circuit paths to said output circuit paths, and control or triggering lines leading from said control or triggering means to said switching elements, the improvement wherein: said switching elements are respectively connected in pairs and are arranged between every second input or output circuit path, said switching elements which have been connected together in pairs being connected together to the adjacent input line with one of their terminals and being connected individually to a respective one of the adjacent output lines with their other terminal.
Claim 2
Dependent Claim
157 words
In a monolithically integrated semiconductor circuit arrangement, particularly for switching matrices of tele-communications switching systems, including a plurality of semiconductor switching elements arranged in a matrix, a plurality of intersecting input and output circuit paths which are arranged in rows and columns and which may be selectively connected together by means of said switching elements, control or triggering means for switching on or blocking said switching elements to selectively connect said input circuit paths to said output circuit paths, and control or triggering lines leading from said control or triggering means to said switching elements, the improvement wherein: said switching elements are respectively connected in pairs and are arranged between every second input or output circuit path, said switching elements which have been connected together in pairs being connected together to the adjacent input line with one of their terminals and being connected individually to a respective one of the adjacent output lines with their other terminal.
Claim 3
Dependent Claim
51 words
A circuit arrangement as defined in claim 1, wherein said control or triggering lines and said control or triggering means for switching on or blocking of the switching elements are arranged in a column between every two columns of said pairs of switching elements in order to increase the screening effect.
Claim 4
Dependent Claim
39 words
A circuit arrangement as defined in claim 2, wherein such control means for switching on or blocking of the switching elements comprise monolithically integrated inverter circuits comprise which are arranged in the immediate vicinity of the associated switching elements.
Claim 5
Dependent Claim
28 words
A circuit arrangement as defined in claim 3, wherein an inverter circuit is provided for each of the two switching elements in a cross point for balanced transmission.
Claim 6
Dependent Claim
24 words
A circuit arrangement as defined in claim 4, further comprising a single crosspoint state store for each crosspoint for controlling the two associated inverters.
Claim 7
Dependent Claim
28 words
A circuit arrangement as defined in claim 3, wherein said inverter circuit comprises a driving transistor of the enhancement type and a load transistor of the depletion type.
Claim 8
Dependent Claim
32 words
A circuit arrangement as defined in claim 6, wherein an MOS transistor of the depletion type constitutes said load transistor with at least the threshold voltage produced by an ion implantation process.
Claim 9
Dependent Claim
40 words
A circuit arrangement as defined in claim 1, wherein said switching elements comprise MOS transistors with a large relationship of channel width to channel length and source and drain regions determining the channel length which are interlaced in meander form.
Claim 10
Dependent Claim
24 words
A circuit arrangement as defined in claim 8, wherein said two switching elements connected together with a common electrode terminal comprise a geometric unit.
Claim 11
Dependent Claim
28 words
A circuit arrangement as defined in claim 8, wherein said MOS transistors have a ratio of channel width to channel length not substantially below a value of 1000.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-27 | 1981-09-26 | 1982-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-27 | 1985-09-26 | 1986-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-27 | 1989-09-26 | 1990-03-28 | $7700.00 | Window Closed / Lapsed |