Sensor data input by means of analog to pulse width-to digital converter

Claim 2

A digital processing system comprising: digital processor means for generating output signals in response to digital input signals, said digital processor means further including means for generating interrogation signals in the form of a transition between a pair of signal levels which are significantly different; at least two sensor means disposed at remote locations for generating analog signals having a value indicative of sensed inputs; first pulse width converter means disposed at one of said remote locations and receiving analog signals from one of said sensor means for generating a first pulse width signal in response to each of said interrogation signals, said first pulse width signal formed by a transition between said same pair of signal levels and having a pulse width indicative of the value of the analog signal received from said one sensor means; second pulse width converter means disposed at the other remote locations and receiving analog signals from the other of said sensor means for generating second pulse width signal a predetermined time after the occurrence of each interrogation signal, said second pulse width signal formed by a transition between said same pair of signal levels and having a pulse width indicative of the value of the analog signal received from said other sensor means; digital converter means interfacing said digital processor and receiving the pulse width signals from said first and second pulse width converter means and said interrogation signals for generating digital data for said digital processor means, said digital data indicative of the pulse width of the received pulse width signals; and a single bi-directional data transmission line for transmitting said interrogation and said pulse width signals between said first and second pulse width converter means and said digital converter means; wherein said first and second pulse width converter means each comprises: bi-stable means switchable between two stable states for switching to a first state and generating a first signal having a signal level the same as one of said pair of signal levels in response to said interrogation signals and for switching to a second state and generating a second signal having a signal level the same as the other of said pair of signal levels in response to a reset signal, wherein said first signal is said pulse width signal; means enabled by said first signal and disabled by said second signal for integrating the analog signal generated by said sensor means to generate an integrated signal having a value proportional to the value of said analog signal and the time of integration; means enabled by said first signal for generating said reset signal each time said integrated signal exceeds a predetermined value; and pulse width signal isolation means interfacing said bi-directional data transmission line for isolating said bi-stable means from the signals on said bi-directional data transmission line for a predetermined interval after receiving said interrogation signal; and wherein said second pulse width converter means further includes: delay means for delaying for said predetermined time the switching of said bi-stable means to said first state in response to said interrogation signals.

Claim 3

The system of claim 1 wherein said first and second pulse width converter means further includes electrical power storage means storing electrical power during the transmission of said interrogation signals for providing electrical power to said first and second pulse width converter means for the generation of said pulse width signals and wherein said digital converter means further includes a driver amplifier increasing the electrical power of said interrogation signals to a value sufficient to fully charge said electrical power storage means.

Claim 4

The system of claim 1 wherein said digital converter means comprises: clock means for generating clock signals having pulse intervals substantially shorter than the minimum width of said pulse width signals; digital means for generating said digital data in response to said clock signals; said digital data indicative of the number of clock signals received; and control means for controlling the number of clock signals received by said digital means, said control means enabled in response to said pulse width signals to transmit said clock signals to said digital means and disabled by said interrogation signal blocking the transmission of said clock signals to said digital means.

Claim 5

The system of claim 3 wherein said at least two sensor means is a plurality of sensors and a like plurality of pulse width converter means wherein one of said plurality of pulse width converter means is a first pulse width converter means and the remaining pulse width converter means are second pulse width converter means wherein the delay means in each successive second pulse width converter means delays the switching of the associated bi-stable multivibrator means a time longer than the delay time of the delay means of the preceding pulse converter means so that the pulse width signals generated by successive pulse width converter means are generated in a predetermined sequential order and wherein each of said pulse width signal isolation means isolates said bi-stable multivibrator means from the signals on said bi-directional data transmission line for a time period sufficient to permit all of said plurality of pulse width converter means to complete the generation of said pulse width signal in said sequential order.

Claim 6

The system of claim 4 wherein each of said plurality of pulse width converter circuits includes electrical power storage means storing electrical power during the transmission of said interrogation signals for providing power for the generation of said binary pulse width signals to said first and second pulse width converter means and wherein said digital converter means further includes a power amplifier increasing the electrical power of said interrogation signals to a value sufficient to fully charge all of said electrical power storage means.

Claim 7

In combination with a digital processing system having at least two sensors disposed at remote locations generating analog signals in response to sensed inputs and a digital processor for generating output signals in response to digital input signals, said digital processor means further including means for generating interrogation signals indicative of a transition from a second signal level to a first signal level substantially different from said second signal level, an improved analog to digital data conversion and data transmission network comprising: first pulse width generating means disposed at one of said remote locations and enabled by each of said interrogation signals for integrating the analog signals generated by one of said at least two sensors to generate a first pulse width signal having a pulse width equal to the time required for the integrated value of the received analog signals to reach a predetermined value, said first pulse width signal formed by a transition from said same second signal level to said same first signal level; second pulse width generator means disposed at the other of said remote locations and enabled by said interrogation signals for integrating the analog signals generated by said other sensor to generate a predetermined time after the occurrence of each of said interrogation signals, a second pulse width signal having a pulse width equal to the time required for the integrated value of the received analog signals to reach a predetermined value, said second pulse width signals formed by a transition from said same second signal level to said same first signal level; digital data generator means interfacing said digital processor and receiving said pulse width signals from said first and second pulse width generator means and said interrogation signals for generating said digital data, said digital data indicative of the pulse width of said pulse width signals; and a single bi-directional data transmission line for transmitting said interrogation and pulse width signals between said first and second pulse width generator means and said digital data generator means; wherein said first and second pulse width generator means each comprises: bi-stable means switchable between two stable states for switching to a first state and generating a first signal having a signal level the same as said first signal level in response to said interrogation signals and for switching to a second state and generating a second signal having a signal level the same as said second signal level in response to a reset signal, wherein said first signal is said pulse width signal; means enabled by said first signal and disabled by said second signal for integrating the analog signal generated by the sensors to generate an integrated signal having a value proportional to the value of said analog data and the time of integration; means enabled by said first signal for generating said reset signal each time said integrated signal exceeds a predetermined value; pulse width signal isolation means interfacing said bi-directional data transmission line for isolating said bi-stable means from the pulse width signals on said bi-directional data transmission line for a predetermined interval after said interrogation signal; and wherein said second pulse width generator means further includes delay means for delaying for said predetermined time the switching of said bi-stable means to said first state in response to said interrogation signals.

Claim 8

In combination with a digital processing system having at least two sensors disposed at remote locations generating analog signals in response to sensed inputs and a digital processor for generating output signals in response to digital input signals, said digital processor means further including means for generating interrogation signals indicative of a transition from a second signal level to a first signal level substantially different from said second signal level, an improved analog to digital data conversion and data transmission network comprising: first pulse width generating means disposed at one of said remote locations and enabled by each of said interrogation signals for integrating the analog signals generated by one of said at least two sensors to generate a first pulse width signal having a pulse width equal to the time required for the integrated value of the received analog signals to reach a predetermined value, said first pulse width signal formed by a transition from said same second signal level to said same first signal level; second pulse width generator means disposed at the other of said remote locations and enabled by said interrogation signals for integrating the analog signals generated by said other sensor to generate a predetermined time after the occurrence of each of said interrogation signals, a second pulse width signal having a pulse width equal to the time required for the integrated value of the received analog signals to reach a predetermined value, said second pulse width signals formed by a transition from said same second signal level to said same first signal level; digital data generator means interfacing said digital processor and receiving said pulse width signals from said first and second pulse width generator means and said interrogation signals for generating said digital data, said digital data indicative of the pulse width of said pulse width signals; and a single bi-directional data transmission line for transmitting said interrogation and pulse width signals between said first and second pulse width generator means and said digital data generator means; wherein said first and second pulse width generator means each comprises: bi-stable means switchable between two stable states for switching to a first state and generating a first signal having a signal level the same as said first signal level in response to said interrogation signals and for switching to a second state and generating a second signal having a signal level the same as said second signal level in response to a reset signal, wherein said first signal is said pulse width signal; means enabled by said first signal and disabled by said second signal for integrating the analog signal generated by the sensors to generate an integrated signal having a value proportional to the value of said analog data and the time of integration; means enabled by said first signal for generating said reset signal each time said integrated signal exceeds a predetermined value; pulse width signal isolation means interfacing said bi-directional data transmission line for isolating said bi-stable means from the pulse width signals on said bi-directional data transmission line for a predetermined interval after said interrogation signal; and wherein said second pulse width generator means further includes delay means for delaying for said predetermined time the switching of said bi-stable means to said first state in response to said interrogation signals.

Claim 9

The combination of claim 6 wherein said first and second pulse width generator means further include electrical power storage means storing electrical power during the transmission of said interrogation signals for providing electrical power to said first and second pulse width converter means for the generation of said pulse width signals and wherein said digital data generator means further include a driver amplifier increasing the electrical power of said interrogation signals to a value sufficient to fully charge said electrical power storage means.

Claim 10

The combination of claim 6 wherein said digital data generator means comprises: clock means for generating clock signals having pulse intervals substantially shorter than the minimum width of said pulse width signals; digital means for generating said digital data in response to said clock signals, said digital data indicative of the number of said clock signals received; and control means for controlling the number of said clock signals received by said digital means, said control means enabled in response to said pulse width signals to transmit said clock signals to said digital means and disabled by said interrogation signal blocking the transmission of said clock signals to said digital means.

Claim 11

The combination of claim 8 wherein said control means comprises: buffer means for transmitting said interrogation signals from said digital processor means to said bi-directional data transmission line; means electrically disposed between said digital processor means and said buffer means for generating an inhibit signal in response to said interrogation signals; means in circuit relationship with said clock means, said digital means, said means for generating said inhibit signal and said bi-directional data transmission line for transmitting said clock signals to said digital means in response to said pulse width signals and for blocking the transmission of said clock signals to said digital means during the occurrence of an interrogation signal in response to said inhibit signal.

Claim 12

The system of claim 9 wherein said pulse width signal isolation means comprises: a first monostable multivibrator having a stable state generating a first output signal and switchable to an unstable state generating a second output signal in response to said interrogation signal, said first monostable mulivibrator remaining in said unstable state for a predetermined isolation period of time; gate circuit means having a first input gate in circuit relationship with said bi-directional data transmission line, and a second input gate in circuit relationship with the output from said first monostable multivibrator for transmitting signals from said bi-directional data transmission line in response to the first signal generated by said first monostable mulivibrator and for blocking the signals from said bi-directional data transmission line in response to the second signal generated by said first monostable multivibrator; and wherein said delay means is a second monostable multivibrator having a stable state generating a first signal and an unstable state generating said delayed interrogation signal, said second monostable being switched to its second state in response to said interrogation signal transmitted by said gate means and remaining in said second state for said predetermined delay time.

Claim 13

The combination of claim 10 wherein said interrogation signals are pulse signals having a leading edge and a trailing edge, said first and second monostable multivibrators are switched to said unstable state by the trailing edge of said interrogation signals.

Claim 14

The combination of claim 11 wherein said digital processor generates said interrogation signals at predetermined time intervals, said first monostable multivibrator remains in said second state for a time period longer than said predetermined delay period plus the maximum duration of the pulse width signal generated by said one first conversion means and shorter than the predetermined time interval between said interrogation signals.

Claim 15

The combination of claim 12 wherein said at least two sensors comprises a plurality of sensors and a like plurality of pulse width generator means wherein one of said plurality of pulse width generator means is a first pulse width generator and the remaining pulse width generator means are said second pulse width generator means, wherein the delay means of each successive second pulse width generator means delays the switching of the associated bi-stable multivibrator for a time longer than the delay time of the delay means of the preceding pulse width generator means so that the pulse width signals generated by successive pulse width generator means are generated in a predetermined sequential order and wherein each of said pulse width signal isolation means isolates said bi-stable multivibrator means from the signals on said bi-directional data transmission line for a time period sufficient to permit all of said plurality of first converter means to complete the generation of said pulse width signal.

Claim 16

The combination of claim 13 wherein each of said first and second pulse width generator means further includes electrical power storage means receiving electrical power from said bi-directional data transmission line for providing power from the generation of said pulse width signals and wherein said digital data generator means further includes a power amplifier increasing the electrical power of said interrogation signals to a value sufficient to fully charge all of said electrical power storage means.

Claim 17

The system of claim 14 wherein each of said storage means comprises: a diode having an anode connected to said bi-directional data transmission line and a cathode; and a storage capacitance having one electrode connected to the cathode of said diode and to said bi-stable multivibrator and having the other electrode connected to a ground potential.

Claim 18

An analog-to-pulse width-to-digital converter and data transmission circuit responsive to interrogation signals indicative of a transition between a pair of signal levels which are significantly different comprising: first means enabled by each interrogation signal for converting analog signals generated by a first source to pulse width signals said pulse width signals having pulse widths indicative of the value of the received analog signals and formed by a transition between the same pair of signal levels as the interrogation signals; at least one second means enabled by each interrogation signal for converting analog signals generated by at least one other source to pulse width signals a predetermined time after receiving said interrogation signal, said pulse width signals having pulse widths indicative of the value of the received analog signals and formed by a transition between the same pair of signal levels as the interrogation signals; third means receiving said pulse width signals and said interrogation signals for generating digital data indicative of the pulse width of the pulse width signals generated by said first and said at least one second means; and a single bi-directional data transmission line for transmitting said interrogation and said pulse width signals between said first, second and third means; and wherein said first and said at least one second means each comprises: bi-stable means switchable between two stable states for switching to a first state and generating a first signal having a signal level the same as one of said pair of signal levels in response to said interrogation signals and for switching to a second state and generating a second signal having a signal level the same as the other of said pair of signal levels in response to a reset signal, wherein said first signal is said pulse width signal; means enabled by said first signal and disabled by said second signal for integrating said analog signal to generate an integrated signal having a value proportional to the value of said analog data and the time of integration; means enabled by said first signal for generating said reset signal each time said integrated signal exceeds a predetermined value; pulse width signal isolation means interfacing said bi-directional data transmission line for isolating said bi-stable means from the pulse width signals generated on said bi-directional data transmission line for a predetermined time after receiving an interrogation signal; and wherein each of said at least one second means further includes: a delay means for delaying for a predetermined period the switching of said bi-stable means to said first state in response to an interrogation signal.

Claim 19

An analog-to-pulse width-to-digital converter and data transmission circuit responsive to interrogation signals indicative of a transition between a pair of signal levels which are significantly different comprising: first means enabled by each interrogation signal for converting analog signals generated by a first source to pulse width signals said pulse width signals having pulse widths indicative of the value of the received analog signals and formed by a transition between the same pair of signal levels as the interrogation signals; at least one second means enabled by each interrogation signal for converting analog signals generated by at least one other source to pulse width signals a predetermined time after receiving said interrogation signal, said pulse width signals having pulse widths indicative of the value of the received analog signals and formed by a transition between the same pair of signal levels as the interrogation signals; third means receiving said pulse width signals and said interrogation signals for generating digital data indicative of the pulse width of the pulse width signals generated by said first and said at least one second means; and a single bi-directional data transmission line for transmitting said interrogation and said pulse width signals between said first, second and third means; and wherein said first and said at least one second means each comprises: bi-stable means switchable between two stable states for switching to a first state and generating a first signal having a signal level the same as one of said pair of signal levels in response to said interrogation signals and for switching to a second state and generating a second signal having a signal level the same as the other of said pair of signal levels in response to a reset signal, wherein said first signal is said pulse width signal; means enabled by said first signal and disabled by said second signal for integrating said analog signal to generate an integrated signal having a value proportional to the value of said analog data and the time of integration; means enabled by said first signal for generating said reset signal each time said integrated signal exceeds a predetermined value; pulse width signal isolation means interfacing said bi-directional data transmission line for isolating said bi-stable means from the pulse width signals generated on said bi-directional data transmission line for a predetermined time after receiving an interrogation signal; and wherein each of said at least one second means further includes: a delay means for delaying for a predetermined period the switching of said bi-stable means to said first state in response to an interrogation signal.

Claim 20

The system of claim 16 wherein said first and at least one second means each further include electrical power storage means storing electrical power during the transmission of said interrogation signals for providing electrical power to said first and said at least one second means after the termination of said interrogation signal for the generation of said pulse width signals and wherein said second converter means further includes a driver amplifier increasing the electrical power of said interrogation signals to a value sufficient to fully charge said electrical power storage means.

Claim 21

The system of claim 16 wherein said third means comprises: clock means for generating clock signals having pulse intervals substantially shorter than the minimum width of said pulse width signals; digital means for generating said digital data in response to said clock signals, said digital data indicative of the number of said clock signals received; and control means for controlling the number of said clock signals received by said digital means, said control means enabled in response to said pulse width signals to transmit said clock signals to said digital means and disabled by said interrogation signal blocking the transmission of said clock signals to said digital means.

Claim 22

The system of claim 18 wherein said control means comprises: buffer means for transmitting said interrogation signals from said digital processor means to said bi-directional data transmission line; means electrically disposed between said digital processor means and said buffer means for generating an inhibit signal in response to said interrogation signals; and means in circuit relationship with said clock means, said digital means, said means for generating said inhibit signal and said bi-directional data transmission line for transmitting said clock signals to said digital means in response to said binary pulse width signals and for blocking the transmission of said clock signals to said digital means during the occurrence of an interrogation signal in response to said inhibit signal.

Claim 23

The system of claim 19 wherein said means for generating an inhibit signal is an inverter amplifier generating an inverted signal indicative of the binary complement of said interrogation signal; and said means for transmitting and blocking is an AND gate having an output terminal connected to said digital means, said AND gate receiving said clock signals at a first input gate, receiving said binary pulse width signals from said bi-directional data transmission line at a second input gate and receiving said inhibit signal at a third input gate.

Claim 24

The system of claim 20 wherein said first and said at least one second means each further includes electrical power storage means receiving electrical power from said bi-directional data transmission line for providing electrical power for the generation of said binary pulse signals, and said buffer means is a driver amplifier increasing the electrical power of said interrogation signals to a value sufficient to fully charge said electrical power storage means.

Claim 25

The system of claim 21 wherein said isolation means comprises: a first monostable multivibrator having a stable state generating a first output signal and switchable to an unstable state generating a second output signal in response to said interrogation signal, said first monostable multivibrator remaining in said unstable state for a predetermined isolation period of time; gate circuit means having a first input gate in circuit relationship with said bi-directional data transmission line, and a second input gate in circuit relationship with the output from said first monostable multivibrator for transmitting signals from said bi-directional data transmission line in response to the second signal generated by said first monostable multivibrator; and wherein said delay means is a second monostable multivibrator having a stable state generating a first signal and an unstable state generating said delayed interrogation signal, said second monostable being switched to its second state in response to said interrogation signal transmitted by said gate means and remaining in said second state for said predetermined delay time.

Claim 26

The system of claim 22 wherein said interrogation signal is a pulse signal having a leading edge and a trailing edge, said bi-stable multivibrator and said first and second monostable multivibrators are switched by the trailing edge of said interrogation signals.

Claim 27

The system of claim 23 wherein said digital processor generates said interrogation signals at predetermined time intervals, said first monostable multivibrator remains in said second state for a time period longer than said predetermined delay period plus the maximum duration of the binary pulse width signal generated by said first means and shorter than the predetermined time interval between said interrogation signals.

Claim 28

The system of claim 24 wherein said at least one second means is a plurality of second means receiving analog signals from a like plurality of other sensors wherein the delay means of each successive second means delays the switching of the associated bi-stable means for a time longer than the delay time of the preceding second means so that the pulse width signals generated by the first and second means occur in a predetermined sequential order; and wherein each of said pulse width signal isolation means isolates said bi-stable multivibrator means from the signals on said bi-directional data transmission line for a time period sufficient to permit said first and said plurality of second means to complete the generation of said binary pulse width signal.

Claim 29

The system of claim 25 wherein each of said first and second means includes electrical power storage means receiving electrical power from said bi-directional data transmission line for providing power for the generation of said pulse width signals and wherein said third means further includes a power amplifier increasing the electrical power of said interrogation signals to a value sufficient to fully charge all of said electrical power storage means.

Claim 30

The system of claim 26 wherein each of said storage means comprises: a diode having an anode connected to said bi-directional data transmission line and a cathode; and a storage capacitance having one electrode connected to the cathode of said diode and to said bi-stable multivibrator and having the other electrode connected to a ground potential.

Claim 33

The method of claim 28 wherein said step of generating interrogation signals includes the step of amplifying said interrogation signals to provide sufficient electrical power to power said first and said second converter means, and said steps of enabling said first and said second converter means includes the step of storing electrical power for the operation of said first and second converter means in an electrical power storage means during the generation of said interrogation signal.