US4075827A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Adjustable circuit for an electronic timepiece
Assignee: Citizen Watch Co Ltd
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Filing: 1976-07-23
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Granted: 1978-02-28
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Expires: 1996-07-23
Abstract
Abstract An adjustable circuit for an electronic timepiece including a crystal oscillator, a frequency divider circuit, a display and a controlable means for increasing and decreasing the output frequency of the frequency divider circuit. The increasing and decreasing means includes a digital adder and a digital subtractor and a plurality of controlable gates for enabling the digital adder or subtractor to increase or decrease the output frequency of the frequency divider.
Inventors
- 👤 Makoto Yoshida
- 👤 Yoshifumi Mochizuki
- 👤 Masamichi Yamauchi
- 👤 Hideyuki Kawashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:10
CPC Classifications
G; G04; G04G; G04G3/00; G04G3/02; G04G3/022; G04G5/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
88 words
A circuit for an electronic timepiece of the type having a piezo-electric reference oscillator, an oscillator circuit coupled to said reference oscillator for producing an electrical oscillation of a predetermined frequency, a divider circuit that divides the frequency of said oscillation, and a driving circuit which drives a display unit using the output of said divider circuit, characterized by the inclusion in said divider circuit of an adder circuit comprising an adder gate and a subtraction circuit comprising a subtraction gate arranged in series with said adder circuit.
Claim 2
Dependent Claim
88 words
A circuit for an electronic timepiece of the type having a piezo-electric reference oscillator, an oscillator circuit coupled to said reference oscillator for producing an electrical oscillation of a predetermined frequency, a divider circuit that divides the frequency of said oscillation, and a driving circuit which drives a display unit using the output of said divider circuit, characterized by the inclusion in said divider circuit of an adder circuit comprising an adder gate and a subtraction circuit comprising a subtraction gate arranged in series with said adder circuit.
Claim 3
Dependent Claim
36 words
A timepiece circuit according to claim 1, further comprising a frequency adjustment pin coupled to said gates which combined with a plurality of existing pins for other functions, can provide for three types of frequency adjustment.
Claim 4
Dependent Claim
25 words
A timepiece circuit according to claim 2, in which the said pins used for other functions are output pins for driving a pulse motor coil.
Claim 5
Dependent Claim
16 words
A timepiece circuit according to claim 2, in which said output pins are electrical source terminals.
Claim 6
Dependent Claim
29 words
A timepiece circuit according to claim 2, which has frequency adjustment values that are determined by combinations of a number of operations of the said adder and subtracter gates.
Claim 7
Dependent Claim
28 words
A timepiece circuit according to claim 5, in which the said values of frequency adjustment are 0 and ±15 PPM × 2 n (where n is an integer).
Claim 8
Dependent Claim
28 words
A timepiece circuit according to claim 4, in which the said gates for addition and subtraction are inserted just ahead of the first stage of the divider circuit.
Claim 9
Dependent Claim
28 words
A timepiece circuit according to claim 3, in which the said gates for addition and subtraction are inserted between the first and second stages of the divider circuit.
Claim 10
Dependent Claim
17 words
A timepiece circuit according to claim 1, in which the said adder gate is an EXCLUSIVE-OR gate.
Claim 11
Dependent Claim
28 words
A timepiece circuit according to claim 1, in which the timing signal which operates said adder gate is different from the timing signal which operates said subtractor gate.
Claim 12
Dependent Claim
18 words
A timepiece circuit according to claim 1, in which the addition and subtraction processes terminate in two seconds.
Claim 13
Dependent Claim
26 words
A timepiece circuit according to claim 3, in which the said frequency assignment pin is located between two of said output pins of an integrated circuit.
Claim 14
Dependent Claim
130 words
A frequency adjustable circuit for an electronic timepiece comprising: a crystal oscillator circuit for producing a periodic signal having a fixed frequency; a frequency divider circuit for dividing the frequency of said periodic signal; a display for displaying the time; a display driver circuit for driving said display with time signals derived from said divided periodic signal; and a controllable means coupled to said frequency divider circuit for increasing and decreasing the frequency of said divided periodic signal, said controllable means comprising: an adder circuit coupled to said frequency divider circuit; a subtracter circuit coupled in series with said adder circuit to said frequency divider circuit; and a plurality of controllable logic gates for enabling said adder or subtracter to increase or decrease the frequency of said divided periodic signal.
Claim 15
Dependent Claim
130 words
A frequency adjustable circuit for an electronic timepiece comprising: a crystal oscillator circuit for producing a periodic signal having a fixed frequency; a frequency divider circuit for dividing the frequency of said periodic signal; a display for displaying the time; a display driver circuit for driving said display with time signals derived from said divided periodic signal; and a controllable means coupled to said frequency divider circuit for increasing and decreasing the frequency of said divided periodic signal, said controllable means comprising: an adder circuit coupled to said frequency divider circuit; a subtracter circuit coupled in series with said adder circuit to said frequency divider circuit; and a plurality of controllable logic gates for enabling said adder or subtracter to increase or decrease the frequency of said divided periodic signal.
References Cited (Backward Citations)
US3841081A
Cited
US3967442A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-27 | 1981-08-29 | 1982-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-27 | 1985-08-29 | 1986-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-27 | 1989-08-29 | 1990-02-28 | $7700.00 | Window Closed / Lapsed |