Error correction of digital signals

Claim 3

A method as set forth in claim 1, further comprising the step of using said first error control bits to correct the second error control bits and information bits prior to performance of said selected correction algorithm.

Claim 4

A method as set forth in claim 1, wherein the step of decoding the second error control bits comprise carrying out a predetermined number of tests, each test utilising selected second error control bits and indicating whether or not correction for a particular information bit is required, the step of defining the correction algorithm comprises determining a reliability rating for each test using the error probability determined from the error control bits, and the step of correcting the information bits comprises using the algorithm to determine from the tests whether or not to correct the particular information bit.

Claim 5

A method as set forth in claim 3, further including dividing the received signal into bytes, and wherein the step of decoding said first error control bits comprises determining a respective error probability for each byte, and the reliability rating for each test is determined from the error probability ratings of the bytes in which second error control bits used in the test appear.

Claim 6

A method as set forth in claim 3, wherein said second error control code is a convolutional check code and the tests are convolutional code check sums.

Claim 7

A method as set forth in claim 5, wherein said first error control code is a parity check code.

Claim 8

A method as set forth in claim 4, wherein the error probability rating for a byte can be good, fair or bad, where the rating good is given to an error free byte, the rating fair is given to a byte containing exactly one bit in error, and the rating bad is given to a byte containing two or more bits in error.

Claim 9

A method as set forth in claim 7, wherein the reliability rating for a test can be good, fair or bad, where the rating good is given to a test the second error control bits of which all appear in bytes rated good, the rating fair is given to a test the second error control bits of which all appear in bytes rated good or fair but not all good, and the rating bad is given to all other tests.

Claim 10

A method as set forth in claim 3, wherein the correction algorithm includes determining whether there are more indications that a particular information bit is incorrect than there are that it is correct, the step of defining the correction algorithm comprising selecting the tests for use as indications according to their reliability ratings.

Claim 11

Apparatus for correcting errors in a digital signal, the apparatus comprising: input means to receive a digital signal comprising information bits, first error control bits corresponding to a first error control code, and second error control bits corresponding to a second error control code, first decoding means connected to the input means to decode the first error control bits to determine the probability of error in the received signal, second decoding means connected to the input means to decode the second error control bits, algorithm -- defining means connected to the output of the first decoding means to define a correction algorithm using the error probability determined from the first error control bits, and correction means connected to the algorithm-defining means, the second decoding means and the input means to correct the information bits by performing on them the said correction algorithm using the decoded second error control bits.

Claim 12

Apparatus for correcting errors in a digital signal, the apparatus comprising: input means to receive a digital signal comprising information bits, first error control bits corresponding to a first error control code, and second error control bits corresponding to a second error control code, first decoding means connected to the input means to decode the first error control bits to determine the probability of error in the received signal, second decoding means connected to the input means to decode the second error control bits, algorithm -- defining means connected to the output of the first decoding means to define a correction algorithm using the error probability determined from the first error control bits, and correction means connected to the algorithm-defining means, the second decoding means and the input means to correct the information bits by performing on them the said correction algorithm using the decoded second error control bits.

Claim 13

Apparatus as set forth in claim 10, further comprising additional correction means having an input connected to the input means, the first decoding means, and the second decoding means and an output connected to the first-mentioned correction means and operative to correct said second error control bits and said information bits using said first error control bits.

Claim 14

Apparatus as set forth in claim 10, wherein said input means comprises byte-defining means to divide the received signal into bytes.

Claim 15

Apparatus as set forth in claim 10, wherein said first decoding means comprises parity check means to carry out a parity check on the first error control bits.

Claim 16

Apparatus as set forth in claim 10, wherein said second decoding means comprises convolutional code check means to carry out convolutional code check sums on the second error control bits.

Claim 17

Apparatus as claimed in claim 13, wherein said parity check means comprises shift register means and logic gate means connected to selected stages of said shift register means.

Claim 18

Apparatus as claimed in claim 14, wherein said convolutional code check means comprises shift register means and logic gate means connected to selected stages of said shift register means.

Claim 19

A data transmission system comprising in combination a. a transmitter including encoding apparatus for coding a digital signal for error correction on reception comprising: transmitter input means to receive information bits to be trasmitted, first error control bit inserting means connected to said transmitter input means to add to the information bits first error control bits corresponding to a first error control code and decodable on reception to determine the probability of error in the received signal, second error control bit inserting means connected to said transmitter input means to add to the information bits second error control bits corresponding to a second error control code and decodable on reception so that a correction algorithm defined in accordance with the error probability determined from the first error control bits can be performed on the information bits using the decoded second error control bits, and output means connected to the outputs of the first and second error control bit inserting means, and b. a receiver including correcting apparatus for correcting errors in the coded digital signal, the correcting apparatus comprising: signal input means connected to receive the coded digital signal first decoding means connected to the signal input means to decode the first error control bits to determine the probability of error in the received signal, second decoding means connected to the signal input means to decode the second error control bits, algorithm-defining means connected to the output of the first decoding means to define a correction algorithm using the error probability determined from the first error control bits, and correction means connected to the algorithm-defining means, the second decoding means and the input means to correct the information bits by performing on them the said correction algorithm using the decoded second error control bits.

Claim 20

A data transmission system comprising in combination a. a transmitter including encoding apparatus for coding a digital signal for error correction on reception comprising: transmitter input means to receive information bits to be trasmitted, first error control bit inserting means connected to said transmitter input means to add to the information bits first error control bits corresponding to a first error control code and decodable on reception to determine the probability of error in the received signal, second error control bit inserting means connected to said transmitter input means to add to the information bits second error control bits corresponding to a second error control code and decodable on reception so that a correction algorithm defined in accordance with the error probability determined from the first error control bits can be performed on the information bits using the decoded second error control bits, and output means connected to the outputs of the first and second error control bit inserting means, and b. a receiver including correcting apparatus for correcting errors in the coded digital signal, the correcting apparatus comprising: signal input means connected to receive the coded digital signal first decoding means connected to the signal input means to decode the first error control bits to determine the probability of error in the received signal, second decoding means connected to the signal input means to decode the second error control bits, algorithm-defining means connected to the output of the first decoding means to define a correction algorithm using the error probability determined from the first error control bits, and correction means connected to the algorithm-defining means, the second decoding means and the input means to correct the information bits by performing on them the said correction algorithm using the decoded second error control bits.

Claim 21

A system as set forth in claim 17, wherein said first error control bit inserting means comprises parity check coding means.

Claim 22

A system as set forth in claim 17, wherein said second error control bit inserting means comprises convolutional check coding means.

Claim 23

Apparatus as set forth in claim 17, further comprising additional correction means having an input connected to the input means, the first decoding means, and the second decoding means and an output connected to the first-mentioned correction means and operative to correct said second error control bits and said information bits using said first error control bits.

Claim 24

Apparatus as set forth in claim 17, wherein said input means comprises byte-defining means to divide the received signal into bytes.

Claim 25

Apparatus as set forth in claim 17, wherein said first decoding means comprises parity check means to carry out a parity check on the first error control bits.

Claim 26

Apparatus as set forth in claim 17, wherein said second decoding means comprises convolutional code check means to carry out convolutional code check sums on the second error control bits.

Claim 27

Apparatus as claimed in claim 23, wherein said parity check means comprises shift register means and logic gate means connected to selected stages of said shift register means.

Claim 28

Apparatus as claimed in claim 24, wherein said convolutional code check means comprises shift register means and logic gate means connected to selected stages of said shift register means.