Semiconductor tester

Claim 2

An improved semiconductor junction tester, comprising: a. visual indicator means having two input connections; b. signal generating means having first, second and third output lines, and producing a first known AC voltage between said first and second output lines, and producing a second known AC voltage between said first and third output lines, at least the AC voltage provided between said first and second output lines being variable; c. first impedance means connected between the first output line of said signal generating means and ground; d. means adapted to be connected across a junction to be tested, said adapted means in turn being connected to the tester in such a manner that said junction is in parallel electrically with said first impedance means and such that, in tester operation, an AC test signal is provided across said junction; e. second impedance means connectable between the second output line of said signal generating means and ground, such that said second impedance means, when so connected, is in parallel electrically with said first impedance means; f. third impedance means connectable between the third output line of said signal generating means and ground, such that said third impedance means, when so connected, is in parallel electrically with said first impedance means; and g. means for selectively connecting and disconnecting said third impedance means to the third output line of said signal generating means, wherein, in operation of the tester, a first output signal is developed between said first impedance means and ground for application to one input connection of said indicator means and a second signal output is developed between said second impedance means and ground for application to the other input connection of said indicator means, and wherein said signal generating means is so configured and arranged, and has such an impedance between its first, second and third output lines, and wherein said second and third impedances have such values that (1) in a first operating condition of the tester, wherein said third impedance means is connected, and the AC voltage between the first and second output lines is at a level which is less than the AC voltage between the first and third output lines, an impedance is presented to said junction which is substantially lower than the effective impedance of the circuit in which said junction is connected, and (2) in a second operating condition of the tester, wherein said third impedance means is disconnected, the amplitude of the voltage between the first and second output lines may be increased to a level sufficient to fire said junction and sufficient impedance is presented to said junction to limit the current therethrough to a safe level, whereby a pattern is produced on said visual indicator means which is indicative of the forward and reverse characteristics of said junction.

Claim 3

An apparatus of claim 1, including first and second voltage divider means, wherein said first voltage divider means is connected between said first impedance means and ground for establishing a nominal voltage level for said first signal, and wherein said second voltage divider means is connected between said second impedance means and ground for establishing a nominal voltage level for said second signal.

Claim 4

An apparatus of claim 2, said first and second voltage divider means comprise impedances which are variable in value, corresponding to the operating condition of the tester.

Claim 5

An apparatus of claim 3, wherein said third impedance is approximately 10 ohms.

Claim 6

An apparatus of claim 3, wherein the AC voltage between the first and third output lines of said signal generating means is approximately 6 VAC, and wherein the AC voltage between the first and second output lines of said signal generating means may be at selected levels between 4.5 VAC and 40 VAC.

Claim 7

An apparatus of claim 3, wherein said visual indicator means is an oscilloscope having horizontal and vertical input connections.

Claim 8

An improved semiconductor junction tester, comprising: a. visual indicator means having horizontal and vertical input connections; b. transformer means having a primary winding and a secondary winding, said secondary winding including a common lead and a plurality of secondary leads, including in succession, first, second and third secondary leads and a fourth secondary lead located between said first and second secondary leads; c. common impedance means connected between said common lead and ground for developing a first signal for application to the horizontal input connection of said indicator means; d. means adapted to be connected across a junction to be tested, said adapted means in turn being connected to the tester in such a manner that said junction is in parallel electrically with said common impedance means, and such that an AC test signal is provided across said junction; e. first, second and third impedance means selectively connectable, respectively, between said first, second and third secondary leads and ground for the purpose of developing a second signal for application to the vertical input connection of said indicator means, wherein said first, second and third impedance means, when so connected, are in parallel electrically with said common impedance means; f. fourth impedance means selectively connectable between said fourth secondary lead and ground, said fourth impedance means, when so connected, being in parallel electrically with said common impedance means, wherein said common impedance means has a substantially larger value then said first, second and third impedance means, and wherein said fourth impedance means is substantially smaller in value than said first, second and third impedance means and further is substantially smaller in value than the effective impedance of the circuit in which the junction to be tested is connected; and g. switching means having three operable positions, such that the tester has at least three operating modes, wherein said first and fourth impedance means are connected respectively, to said first and fourth secondary leads when said switching means is in a first position, wherein said second impedance means is connected to said second secondary lead when said switching means is in a second position, and wherein said third impedance means is connected to said third secondary lead when said switching means is in a third position, wherein said tester in operation presents a relatively low voltage and low impedance to the junction under test when said switching means is in said first position, wherein said tester presents a substantially higher voltage and impedance to the junction under test when said switching means is in said second position, and further wherein said tester presents an even higher voltage and impedance to said junction under test when said switching means is in said third position, said common impedance means and said first, second, third and fourth impedance means being selected and arranged so as to limit the current presented to the junction under test to a safe level.

Claim 9

An improved semiconductor junction tester, comprising: a. visual indicator means having horizontal and vertical input connections; b. transformer means having a primary winding and a secondary winding, said secondary winding including a common lead and a plurality of secondary leads, including in succession, first, second and third secondary leads and a fourth secondary lead located between said first and second secondary leads; c. common impedance means connected between said common lead and ground for developing a first signal for application to the horizontal input connection of said indicator means; d. means adapted to be connected across a junction to be tested, said adapted means in turn being connected to the tester in such a manner that said junction is in parallel electrically with said common impedance means, and such that an AC test signal is provided across said junction; e. first, second and third impedance means selectively connectable, respectively, between said first, second and third secondary leads and ground for the purpose of developing a second signal for application to the vertical input connection of said indicator means, wherein said first, second and third impedance means, when so connected, are in parallel electrically with said common impedance means; f. fourth impedance means selectively connectable between said fourth secondary lead and ground, said fourth impedance means, when so connected, being in parallel electrically with said common impedance means, wherein said common impedance means has a substantially larger value then said first, second and third impedance means, and wherein said fourth impedance means is substantially smaller in value than said first, second and third impedance means and further is substantially smaller in value than the effective impedance of the circuit in which the junction to be tested is connected; and g. switching means having three operable positions, such that the tester has at least three operating modes, wherein said first and fourth impedance means are connected respectively, to said first and fourth secondary leads when said switching means is in a first position, wherein said second impedance means is connected to said second secondary lead when said switching means is in a second position, and wherein said third impedance means is connected to said third secondary lead when said switching means is in a third position, wherein said tester in operation presents a relatively low voltage and low impedance to the junction under test when said switching means is in said first position, wherein said tester presents a substantially higher voltage and impedance to the junction under test when said switching means is in said second position, and further wherein said tester presents an even higher voltage and impedance to said junction under test when said switching means is in said third position, said common impedance means and said first, second, third and fourth impedance means being selected and arranged so as to limit the current presented to the junction under test to a safe level.

Claim 10

An apparatus of claim 7, including first and second voltage divider means, wherein said first voltage divider means is connected between said common impedance means and ground for establishing a nominal voltage level for said first signal; and wherein said second voltage divider means is selectively connectable between said first, second and third impedance means and ground for establishing a nominal voltage level for said second signal.

Claim 11

An apparatus of claim 8, wherein said first and second voltage divider means comprise impedances which are variable in value, corresponding to the operating mode of the tester.

Claim 12

An apparatus of claim 9, wherein said primary winding includes a fifth resistance means which assists in limiting the current applied to the junction under test.

Claim 13

An apparatus of claim 9, wherein said common impedance means comprises a third voltage divider which in turn comprises two impedances of substantially equal value.

Claim 14

An apparatus of claim 9, wherein said first secondary lead provides approximately 4.5 VAC, wherein said secondary lead provides approximately 20 VAC, wherein said third secondary lead provides approximately 40 VAC, and wherein said fourth secondary lead provides approximately 6 VAC.

Claim 15

An apparatus of claim 12, wherein said first, second and third impedance means are substantially equal in value.

Claim 16

An apparatus of claim 13, wherein said fourth impedance means is approximately 10 ohms.

Claim 17

An apparatus of claim 14, wherein said first, second and third impedance means are approximately 18 Kohms, and wherein the two impedances comprising said third voltage divider means are 100 Kohms each.