US4072974A
Expired / Lapsed
US
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Silicon resistive device for integrated circuits
Assignee: RCA Corp
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Filing: 1976-11-18
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Granted: 1978-02-07
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Expires: 1996-11-18
Abstract
Abstract A resistive device for use as a current feedback loop in an integrated CMOS shift register circuit is made of an island of polycrystalline silicon with a sheet resistivity of from 10 6 to 10 8 ohms per square. The polycrystalline silicon island has two contacts thereon fashioned in the manner of MOS source and drain contacts and a dummy polycrystalline silicon insulated gate contact thereon. The device structure is designed to be and is fully compatible with CMOS mesa processing. The method for making the device incorporates into the processing steps for CMOS manufacture the formation of polycrystalline silicon islands on the substrate along with monocrystalline silicon islands. In the process, the polycrystalline silicon island is doped, through source and drain mask openings, with impurities of the same conductivity type as that predominating in the polycrystalline silicon island.
Inventors
- 👤 Alfred C. Ipri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:12
CPC Classifications
H; H10; H10D; H10D86/00; G; G11; G11C; G11C19/00; G11C19/28; G11C19/282; G11C19/285; H10D30/00; H10D30/60; H10D30/67; H10D30/6758; H10D30/6759; H10D86/01; H10D86/03; Y; Y10; Y10S; Y10S148/00; Y10S148/15
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
155 words
In an integrated circuit of the type comprising a shift register cell comprised of a first complementary symmetry metal-oxide-semiconductor transmission gate, a first complementary symmetry metal-oxide-semiconductor inverter having a common gate electrode connected to the output of the first gate, a second complementary symmetry metal-oxide-semiconductor transmission gate having an input connected to the output of the first inverter and a second complementary symmetry metal-oxide-semiconductor inverter having a common gate electrode connected to the output of the second complementary symmetry metal-oxide-semiconductor gate, the improvement comprising a resistive device comprised of an island of polycrystalline silicon having three regions of the same conductivity type, two of the regions having a high impurity concentration with conductive contacts connected thereto, the other regions separating the first mentioned regions and having a moderate impurity concentration, the resistive device being connected between the output of the second complementary sgymmetry metal-oxide-semiconductor inverter and the input of the first complementary symmetry metal-oxide-semiconductor inverter.
Claim 2
Dependent Claim
155 words
In an integrated circuit of the type comprising a shift register cell comprised of a first complementary symmetry metal-oxide-semiconductor transmission gate, a first complementary symmetry metal-oxide-semiconductor inverter having a common gate electrode connected to the output of the first gate, a second complementary symmetry metal-oxide-semiconductor transmission gate having an input connected to the output of the first inverter and a second complementary symmetry metal-oxide-semiconductor inverter having a common gate electrode connected to the output of the second complementary symmetry metal-oxide-semiconductor gate, the improvement comprising a resistive device comprised of an island of polycrystalline silicon having three regions of the same conductivity type, two of the regions having a high impurity concentration with conductive contacts connected thereto, the other regions separating the first mentioned regions and having a moderate impurity concentration, the resistive device being connected between the output of the second complementary sgymmetry metal-oxide-semiconductor inverter and the input of the first complementary symmetry metal-oxide-semiconductor inverter.
Claim 3
Dependent Claim
134 words
A resistive device comprising mesa semiconducting means for providing high ohmic electrical resistance, said means comprising two doped regions of a conductivity type, at least two laterally spaced conductive contacts connected respectively to the two regions, said semiconducting means further comprising a channel region of the same conductivity type with less doping concentration, the channel region separating the first said two regions, an insulating means locating adjacent the channel region, a false gate adjacent the insulating means, the false gate being located above the channel region, and an insulating single crystal substrate adjacent the semiconducting means and supporting the semiconducting means, wherein said semiconducting means is comprised of an island of polycrystalline silicon, wherein the first said two regions have a high impurity concentration, and wherein the channel region has a moderate impurity concentration.
Claim 4
Dependent Claim
134 words
A resistive device comprising mesa semiconducting means for providing high ohmic electrical resistance, said means comprising two doped regions of a conductivity type, at least two laterally spaced conductive contacts connected respectively to the two regions, said semiconducting means further comprising a channel region of the same conductivity type with less doping concentration, the channel region separating the first said two regions, an insulating means locating adjacent the channel region, a false gate adjacent the insulating means, the false gate being located above the channel region, and an insulating single crystal substrate adjacent the semiconducting means and supporting the semiconducting means, wherein said semiconducting means is comprised of an island of polycrystalline silicon, wherein the first said two regions have a high impurity concentration, and wherein the channel region has a moderate impurity concentration.
Claim 5
Dependent Claim
106 words
In a silicon-on-sapphire integrated circuit of the type comprising at least one field effect transistor having a source and a drain separate by a channel, a source contact connected to the source, a drain contact connected to the drain, and a gate insulated from and spaced above the channel, the improvement comprising: a resistor device comprising an island of polycrystalline silicon having three regions of the same conductivity type, two of the regions having a high impurity concentration with conductive contacts connected thereto, the other region separating the first mentioned regions and having moderate impurity concentrations, the resistor device being connected to the field effect transistor.
Claim 6
Dependent Claim
106 words
In a silicon-on-sapphire integrated circuit of the type comprising at least one field effect transistor having a source and a drain separate by a channel, a source contact connected to the source, a drain contact connected to the drain, and a gate insulated from and spaced above the channel, the improvement comprising: a resistor device comprising an island of polycrystalline silicon having three regions of the same conductivity type, two of the regions having a high impurity concentration with conductive contacts connected thereto, the other region separating the first mentioned regions and having moderate impurity concentrations, the resistor device being connected to the field effect transistor.
Claim 7
Dependent Claim
220 words
In a silicon-on-sapphire integrated circuit of the type comprising at least one field effect transistor having a source and a drain separated by a channel, a source contact connected to the source, a drain contact connected to the drain, and a gate insulated from and spaced above the channel, the improvement comprising: mesa semiconducting means for providing high ohmic electrical resistance, said means comprising two doped regions of a conductivity type, at least two laterally spaced conductive contacts connected respectively to the two regions, said semiconducting means further comprising a channel region of the same conductivity type with less doping concentration, the channel region separating the first said two regions, and insulating means located adjacent the channel region, a false gate adjacent the insulating means, the false gate being located above the channel region, and an insulating single crystal substrate adjacent the semiconducting means and supporting the semiconducting means, wherein said semiconducting means is comprised of an island of polycrystalline silicon, wherein the first said two regions have a high impurity concentration and the channel region has a moderate impurity concentration, wherein the false gate comprises a first layer of an insulating maferial on said island, a second layer of polycrystalline silicon on the first layer, and a third layer of an insulating material above the first and second layers.
Claim 8
Dependent Claim
220 words
In a silicon-on-sapphire integrated circuit of the type comprising at least one field effect transistor having a source and a drain separated by a channel, a source contact connected to the source, a drain contact connected to the drain, and a gate insulated from and spaced above the channel, the improvement comprising: mesa semiconducting means for providing high ohmic electrical resistance, said means comprising two doped regions of a conductivity type, at least two laterally spaced conductive contacts connected respectively to the two regions, said semiconducting means further comprising a channel region of the same conductivity type with less doping concentration, the channel region separating the first said two regions, and insulating means located adjacent the channel region, a false gate adjacent the insulating means, the false gate being located above the channel region, and an insulating single crystal substrate adjacent the semiconducting means and supporting the semiconducting means, wherein said semiconducting means is comprised of an island of polycrystalline silicon, wherein the first said two regions have a high impurity concentration and the channel region has a moderate impurity concentration, wherein the false gate comprises a first layer of an insulating maferial on said island, a second layer of polycrystalline silicon on the first layer, and a third layer of an insulating material above the first and second layers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-06 | 1981-08-08 | 1982-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-06 | 1985-08-08 | 1986-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-06 | 1989-08-08 | 1990-02-07 | $7700.00 | Window Closed / Lapsed |