US4072364A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Compensating circuit arrangement in a wheel anti-skid brake control system to obtain corresponding measured values of the duration of the half cycle alternations of a wheel generated voltage
Assignee: WABCO WESTINGHOUSE GmbH
•
Filing: 1976-10-18
•
Granted: 1978-02-07
•
Expires: 1996-10-18
Abstract
Abstract In an anti-skid brake control system for a wheeled vehicle, an electronic circuit for generating a wheel speed signal in accordance with the time duration of a half cycle of a sinusoidal waveform generated by a sensor that detects the presence or absence of teeth of a rotor that revolves with a wheel of the vehicle is arranged so that the measured time duration of both a positive and a negative alternation of the waveform is utilized to obtain accurate wheel skid control at relatively low speeds. Slight differences in the measured time duration of a positive and negative half cycle due to slight variations in the dimensions of a tooth and adjacent space are sensed and modified as required to assure correspondence between the measured time durations in order to avoid false sensing of a wheel skid condition.
Inventors
- 👤 Wolfgang Gudat
- 👤 Gerhard Ruhnau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:18
CPC Classifications
B; B60; B60T; B60T8/00; B60T8/17; B60T8/172; G; G01; G01P; G01P15/00; G01P15/16; G01P15/165; G01P3/00; G01P3/42; G01P3/56; G01P3/60
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
193 words
In an anti-skid brake control system for a wheeled vehicle, an electronic circuit for generating a wheel speed signal in accordance with the time duration of a half cycle of a sinusoidal waveform whose positive and negative alternations are provided by a sensor that detects the presence or absence of a tooth of a rotor that revolves with a wheel of the vehicle, said electronic circuit comprising: (a) timing means subject to said sinusoidal waveform for providing a time signal representative of the time duration of a respective one of said positive and negative alternations of said sinusoidal waveform; (b) comparator means for detecting a difference between said time signal of a positive alternation and said time signal of a negative alternation of said sinusoidal waveform; and (c) compensating means for regulating said timing means so as to modify said time signal corresponding to one of said positive and negative alternations of said sinusoidal waveform when said comparator means detects a difference therebetween, whereby said wheel speed signal generated during a positive half cycle and a negative half cycle of said sinusoidal waveform are in correspondence for any given velocity of wheel rotation.
Claim 2
Dependent Claim
193 words
In an anti-skid brake control system for a wheeled vehicle, an electronic circuit for generating a wheel speed signal in accordance with the time duration of a half cycle of a sinusoidal waveform whose positive and negative alternations are provided by a sensor that detects the presence or absence of a tooth of a rotor that revolves with a wheel of the vehicle, said electronic circuit comprising: (a) timing means subject to said sinusoidal waveform for providing a time signal representative of the time duration of a respective one of said positive and negative alternations of said sinusoidal waveform; (b) comparator means for detecting a difference between said time signal of a positive alternation and said time signal of a negative alternation of said sinusoidal waveform; and (c) compensating means for regulating said timing means so as to modify said time signal corresponding to one of said positive and negative alternations of said sinusoidal waveform when said comparator means detects a difference therebetween, whereby said wheel speed signal generated during a positive half cycle and a negative half cycle of said sinusoidal waveform are in correspondence for any given velocity of wheel rotation.
Claim 3
Dependent Claim
126 words
The Electronic circuit recited in claim 1, wherein said timing means comprises: (a) first and second oscillator means for producing a pulsed signal at the respective outputs thereof; (b) first AND gate means enabled during said positive half cycle of said sinusoidal waveform for passing said pulsed output signal from said first oscillator means; (c) second AND gate means enabled during said negative half cycle of said sinusoidal waveform for passing said pulsed output signal from said second oscillator means; and (d) first and second counter means to which said pulsed output signal passed via said first and second AND gate means is connected respectively to provide said time signal representative of the time duration of said positive and said negative alternations of said sinusoidal waveform.
Claim 4
Dependent Claim
143 words
The electronic circuit recited in claim 2, wherein said timing means further comprises: (a) circuit means for converting said sinusoidal waveform into a square shaped alternating voltage waveform at the output thereof; (b) said first AND gate having one input connected to the output of said circuit means and another input connected to the output of said first oscillator means; (c) said second AND gate having one input connected to the output of said circuit means in parallel with the one input of said first AND gate and another input connected to the output of said second oscillator means; and (d) signal inverter means connected intermediate said circuit means and the one input of said second AND gate for inverting the polarity of said square shaped waveform thereat to enable said second AND gate during the negative half cycle of the sinusoidal waveform.
Claim 5
Dependent Claim
112 words
The electronic circuit as recited in claim 3, wherein: (a) said first oscillator means provides said pulsed signal at the output thereof at a predetermined frequency; (b) said second oscillator means provides said pulsed signal at the output thereof at a variable frequency; and (c) said compensating means comprises a voltage storage unit whose voltage potential is varied in response to operation of said comparator means when a difference exists between said time signals corresponding to the duration of said positive and negative alternations of said sinusoidal waveform, said second oscillator means being subject to said variable output voltage of said voltage storage unit to provide said variable frequency pulse signal thereof.
Claim 6
Dependent Claim
31 words
The electronic circuit recited in claim 4, wherein said first and second counter means comprises a first and second digital counter whose outputs provide said time signals in binary code form.
Claim 7
Dependent Claim
78 words
The electronic circuit recited in claim 5, further comprising a first digital register connected between said comparator means and said first counter means for storing said binary coded time signal representing the time duration of the positive half cycle of said sinusoidal waveform and a second digital register connected between said comparator means and said second counter means for storing said binary coded time signal representing the time duration of the negative half cycle of said sinusoidal waveform.
Claim 8
Dependent Claim
104 words
The electronic circuit recited in claim 6, wherein said comparator means is a digital comparator having first and second outputs connected to said voltage regulator, said first or second output being energized responsive to a difference between the binary coded time signals stored in said first and second registers to cause said voltage storage unit to increase or decrease its voltage potential depending upon which of said first and second registers is providing the greater time signal, so as to adjust said variable frequency pulse signal provided by said second oscillator in such sense as to cause said time signals to be in correspondence.
Claim 9
Dependent Claim
36 words
The electronic circuit recited in claim 4, further characterized in that said voltage storage unit is subject to a control signal for withholding further variation of the output voltage thereof whenever a brake application is made.
References Cited (Backward Citations)
US3757167A
Cited
US3937525A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-06 | 1981-08-08 | 1982-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-06 | 1985-08-08 | 1986-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-06 | 1989-08-08 | 1990-02-07 | $7700.00 | Window Closed / Lapsed |