Transistor-transistor-logic circuit

Claim 2

An improved monolithically integrated transistor-transistor-logic circuit comprising: an input transistor having a collector region, a base region, and at least one emitter region connected to an input; an output transistor having a colletor region, a base region, and at least one emitter region; an electrical path coupling the base region of said output transistor to the collector region of said input transistor; a first source of potential electrically coupled by means of a first impedance to the base region of said input transistor and by menas of a second impedance to the collector region of said output transistor; a second source of potential electrically coupled to the emitter region of said output transistor; and circuit means electrically coupled to said base region of said output transistor for biasing said output transistor into a first binary state when said inputtansistor malfunctions by failing to provide a current path for biasing said output transistor into a second binary state; said circuit means electrically coupled to said base region of said output transistor being a high impedance current path comprising a series connected Schottky Barrier Diode and a third impedance.

Claim 3

An improved circuit as in claim 1 wherein an output is taken from the collector region of said output transistor, said circuit further comprising: a unidirectionally conducting means electrically connecting the base region and collector region of said input transistor.

Claim 4

An improved circuit as in claim 2 wherein said unidirectionally conducting means is a Schottky barrier diode.

Claim 5

An improved circuit as in claim 1 wherein said circuit means electrically coupled to said base region of said output transistor is also electrically coupled to said first source of potential providing a high impedance current path between said first source of potential and said base region of said output transistor.

Claim 6

An improved monolithically integrated transistor-transistor-logic circuit comprising: an input transistor having a collector region, a base region, and at least one emitter region connected to an input; an output transistor having a collector region, a base region, and at least one emitter region; an electrical path coupling the base region of said output transistor to the collector region of said input transistor; a first source of potential electrically coupled by means of a first impedance to the base region of said input transistor and by means of a second impedance to the collector region of said output transistor; a second source of potential electrically coupled to the emitter region of said output transistor; and circuit means electrically coupled to said base region of said output transistor for biasing said output transistor into a first binary state when said input transistor malfunctions by failing to provide a current path for biasing said output transistor into a second binary state; said input transistor and said output transistor being NPN transistors; said first source of potential having a more positive value than said second source of potential; and said input transistor having a plurality of emitter regions; said improved circuit providing a NAND logical output function at the collector of said output transistor.

Claim 7

An improved monolithically integrated transistor-transistor-logic circuit comprising: an input transistor having a collector region, a base region, and at least one emitter region connected to an input; an output transistor having a collector region, a base region, and at least one emitter region; an electrical path coupling the base region of said output transistor to the collector region of said input transistor; a first source of potential electrically coupled by means of a first impedance to the base region of said input transistor and by means of a second impedance to the collector region of said output transistor; a second source of potential electrically coupled to the emitter region of said output transistor; and circuit means electrically coupled to said base region of said output transistor for biasing said output transistor into a first binary state when said input transistor malfunctions by failing to provide a current path for biasing said output transistor into a second binary state; said input transistor and said output transistor being NPN transistors; said first source of potential having a more positive value than said second source of potential; and said input transistor having a plurality of emitter regions; said improved circuit providing a NAND logical output function at the collector of said output transistor.

Claim 8

An improved circuit as in claim 5 wherein said means electrically coupled to said base region of said output transistor conducts current only when at least one of the emitter regions of said input transistor is brought to a potential level approximating the value of said second source of potential thereby bringing said electrical path more than one diode voltage drop below the potential level of said first source of potential.

Claim 9

An improved circuit as in claim 5 further comprising: a unidirectionally conducting means electrically connecting the base region and collector region of said input transistor.

Claim 10

An improved circuit as in claim 7 wherein said unidirectionally conducting means is a Schottky Barrier Diode

Claim 11

An improved circuit as in claim 5 wherein said circuit means electrically coupled to said base region of said output transistor is also electrically coupled to said first source of potential providing a high impedance current path between said first source of potential and said base region of said output transistor.

Claim 12

An improved monolithically integrated transistor-transistor-logic circuit wherein the integrated form of said circuit, in part, comprises: a semiconductor body having a substrate doped with impurities of a first conductivity type; an input transistor having a collector region, a base region, and at least one emitter region connected to an input; an output transistor having a collector region, a base region, and at least one emitter region; an electrical path coupling the base region of said output transistor to the collector region of said input transistor; a first source of potential electrically coupled by means of a first impedance to the base region of said input transistor and by means of a second impedance to the collector region of said output transistor; a second source of potential electrically coupled to the emitter region of said output transistor; and circuit means electrically coupled to said base region of said output transistor for biasing said output transistor into a first binary state when said input transistor malfunctions by failing to provide a current path for biasing said output transistor into a second binary state; a first semiconductor region doped with impurities of a second conductivity type buried within said body and forming a subcollector for said input transistor; a second semiconductor region doped with impurities of said first conductivity type disposed over said first semiconductor region, and forming a base region for said input transistor; at least one third semiconductor region doped with impurities of said second conductivity type disposed in said second semiconductor region at its upper surface forming at least one emitter region for said input transistor; a fourth semiconductor region contiguous with said first semiconductor region and doped with impurities of said second conductivity type having a doping concentration less than the doping concentration of said first semiconductor region, thereby providing a semiconductor region of higher resistivity than the resistivity of said first semiconductor region; and said fourth semiconductor region having an electrical connection to said first source of potential.

Claim 13

An improved monolithically integrated transistor-transistor-logic circuit wherein the integrated form of said circuit, in part, comprises: a semiconductor body having a substrate doped with impurities of a first conductivity type; an input transistor having a collector region, a base region, and at least one emitter region connected to an input; an output transistor having a collector region, a base region, and at least one emitter region; an electrical path coupling the base region of said output transistor to the collector region of said input transistor; a first source of potential electrically coupled by means of a first impedance to the base region of said input transistor and by means of a second impedance to the collector region of said output transistor; a second source of potential electrically coupled to the emitter region of said output transistor; and circuit means electrically coupled to said base region of said output transistor for biasing said output transistor into a first binary state when said input transistor malfunctions by failing to provide a current path for biasing said output transistor into a second binary state; a first semiconductor region doped with impurities of a second conductivity type buried within said body and forming a subcollector for said input transistor; a second semiconductor region doped with impurities of said first conductivity type disposed over said first semiconductor region, and forming a base region for said input transistor; at least one third semiconductor region doped with impurities of said second conductivity type disposed in said second semiconductor region at its upper surface forming at least one emitter region for said input transistor; a fourth semiconductor region contiguous with said first semiconductor region and doped with impurities of said second conductivity type having a doping concentration less than the doping concentration of said first semiconductor region, thereby providing a semiconductor region of higher resistivity than the resistivity of said first semiconductor region; and said fourth semiconductor region having an electrical connection to said first source of potential.

Claim 14

An improved monolithicaly integrated transistor-transistor-logic circuit as in claim 10 wherein said electrical connection comprises: a Schottky barrier diode.

Claim 15

An improved monollthically integrated transistor-transitor-logic circuit as in claim 10 wherein said fourth semiconductor region comprises: an epitaxial layer deposited on siad substrate.

Claim 16

An improved monolithically integrated transistor-tranisistor-logic circuit as in claim 10 further comprising: fifth and sixth semiconductor regions doped with impurities of said first conductivity type forming said first and second impedance means, respectively.