§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
US4068295A Expired / Lapsed US ⏱️ 0.0 years remaining

Voltage multiplier for an electronic time apparatus

Assignee: Ebauches SA
•
Filing: 1976-07-06
•
Granted: 1978-01-10
•
Expires: 1996-07-06
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A voltage multiplier for an electronic time-measuring apparatus comprising cells, each of which including two capacitors, a pair of complementary field-effect transistors (FET'S) acting as switches, and an inverter comprising a pair of FET'S. The elements of the cells are such that they are capable of being integrated together with the rest of the circuit of the time-measuring apparatus. The voltage to be increased is fed via a first capacitor to the first pair of FETS'S and at the same time to the input of the inverter whose output drives with the correct phase the first pair of FETS'S, which alternatively switches the input signal to a common point of the cell and to an output terminal of the cell, thus charging a second capacitor with the opposite polarity than that of the input signal respective to the common point of the cell. In order for the input voltage to be further increased, the cells can be cascaded in a chain, the common point of one cell being connected to the output terminal of the preceding cell. Each cell will add to the preceding one an amount of voltage equal to that of the input voltage.

Inventors

  • 👤 Hubert Portmann

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 21:16
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; G; G04; G04G; G04G19/00; G04G19/02; G04G19/04

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 117 words
A voltage multiplier for an electronic time apparatus comprising, at least one cell, including two complimentary field effect transistors, a first capacitor, said first capacitor transmitting an input signal to said two complimentary field effect transistors, said transistors transmitting the input signal alternatively to a common point of the cell and to an output terminal of the cell, a reverser, said transistors being controlled by said reverser, said reverser also being controlled by the signal transmitted to the transistors by said first capacitor and fed by voltages appearing at the common point and at the output terminal of the cell, a second capacitor being connected between the output terminal and a stable voltage point of the cell.
Claim 2
Dependent Claim 117 words
A voltage multiplier for an electronic time apparatus comprising, at least one cell, including two complimentary field effect transistors, a first capacitor, said first capacitor transmitting an input signal to said two complimentary field effect transistors, said transistors transmitting the input signal alternatively to a common point of the cell and to an output terminal of the cell, a reverser, said transistors being controlled by said reverser, said reverser also being controlled by the signal transmitted to the transistors by said first capacitor and fed by voltages appearing at the common point and at the output terminal of the cell, a second capacitor being connected between the output terminal and a stable voltage point of the cell.
Claim 3
Dependent Claim 27 words
A multiplier in accordance with claim 1, in which the transistors of the multiplier are of small dimensions with respect to external transistors providing the input signal.
Claim 4
Dependent Claim 24 words
A multiplier in accordance with claim 1, in which a resistance is connected between the first capacitor and the two transistors of the cell.
Claim 5
Dependent Claim 51 words
A multiplier in accordance with claim 1, in which the stable voltage point of the cell is one of the terminals of a battery for supplying the time apparatus and the output voltage of the multiplier is taken between the output terminal of the cell and a terminal of the battery.
Claim 6
Dependent Claim 54 words
A multiplier in accordance with claim 1, in which several cells are connected in cascade, so that the common point of one cell is connected to the output terminal of the preceding cell, the inputs of each of the cells being common and the stable voltage points of each of the cells being common.

References Cited (Backward Citations)

US3790812A Cited
US3824447A Cited
US3944908A Cited
DE2530870A1 Cited
US4001664A Cited
US4015420A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-01-09 1981-07-11 1982-01-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-01-09 1985-07-11 1986-01-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-01-09 1989-07-11 1990-01-10 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag