US4066915A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory circuit
Assignee: Hitachi Ltd
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Filing: 1976-08-06
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Granted: 1978-01-03
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Expires: 1996-08-06
Abstract
Abstract A memory circuit is comprised of a memory cell of PNPN- equivalent 4-layer construction, a selective input circuit composed of a pair of an NPN transistor and a PNP transistor, and a read-out circuit for reading the information stored in the memory cell. The emitters of the transistors included in the selective input circuit are connected to one of the selective input terminals, the bases thereof to the other selective input terminal, the collector of one of the transistors to the write input terminal of the memory cell, and the collector of the other transistor to the input terminal of the read-out circuit. Thus, both the writing and reading operations are controlled from the same selective input terminal, and power consumption of the selective input circuit in the holding mode is substantially zero.
Inventors
- 👤 Ichiro Ohhinata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:35
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/35; H03K3/352; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/39
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
142 words
A memory circuit comprising a memory cell of PNPN-equivalent 4-layer construction with a write terminal and a read terminal, selective input means composed of a pair of an NPN transistor and PNP transistor, and read-out means having two input terminals for reading information stored in said memory cell, wherein the emitters of said NPN transistor and said PNP transistor included in said selective input means are connected to one of two selective input terminals, the bases of said transistors are connected to the other of said two selective input terminals, the collector of one of said transistors is connected to the write terminal of said memory cell, and the collector of the other transistor is connected to one of the two input terminals of said read-out means and the other input terminal is connected to the read terminal of said memory cell.
Claim 2
Dependent Claim
142 words
A memory circuit comprising a memory cell of PNPN-equivalent 4-layer construction with a write terminal and a read terminal, selective input means composed of a pair of an NPN transistor and PNP transistor, and read-out means having two input terminals for reading information stored in said memory cell, wherein the emitters of said NPN transistor and said PNP transistor included in said selective input means are connected to one of two selective input terminals, the bases of said transistors are connected to the other of said two selective input terminals, the collector of one of said transistors is connected to the write terminal of said memory cell, and the collector of the other transistor is connected to one of the two input terminals of said read-out means and the other input terminal is connected to the read terminal of said memory cell.
Claim 3
Dependent Claim
196 words
A memory circuit comprising a memory cell of PNPN-equivalent 4-layer construction with a write terminal and a read terminal, selective input means composed of a pair of an NPN transistor and a PNP transistor and having two selective input terminals, and read-out means including an NPN transistor and a PNP transistor, the collector of said NPN transistor of said read-out means being connected to a read output terminal, the base of said NPN transistor of said read-out means being connected to the collector of said PNP transistor of said read-out means, the base of said PNP transistor of said read-out means being connected to the read terminal of said memory cell, the emitters of said transistors of said selective input means being connected to one of the two selective input terminals, the bases of said transistors of said selective input means being connected to the other of said selective input terminals, the collector of said NPN transistor of said selective input means being connected to the write terminal of said memory cell, the collector of said PNP transistor of said selective input means being connected to the emitter of said PNP transistor of said read-out means.
Claim 4
Dependent Claim
196 words
A memory circuit comprising a memory cell of PNPN-equivalent 4-layer construction with a write terminal and a read terminal, selective input means composed of a pair of an NPN transistor and a PNP transistor and having two selective input terminals, and read-out means including an NPN transistor and a PNP transistor, the collector of said NPN transistor of said read-out means being connected to a read output terminal, the base of said NPN transistor of said read-out means being connected to the collector of said PNP transistor of said read-out means, the base of said PNP transistor of said read-out means being connected to the read terminal of said memory cell, the emitters of said transistors of said selective input means being connected to one of the two selective input terminals, the bases of said transistors of said selective input means being connected to the other of said selective input terminals, the collector of said NPN transistor of said selective input means being connected to the write terminal of said memory cell, the collector of said PNP transistor of said selective input means being connected to the emitter of said PNP transistor of said read-out means.
Claim 5
Dependent Claim
191 words
A memory circuit comprising a memory cell of PNPN- equivalent 4-layer construction with a write terminal and a read terminal, selective input means composed of a pair of an NPN transistor and a PNP transistor, and read-out means including a PNP transistor and an NPN transistor, the collector of said PNP transistor of said read-out means being connected to a read output terminal, the base of said PNP transistor of said read-out means being connected to the collector of said NPN transistor of said read-out means, the base of said NPN transistor of said read-out means being connected to the read terminal of said memory cell, the emitters of said transistors of said selective input means being connected to one of two selective input terminals, the bases of said transistors of said selective input means being connected to the other of said two selective input terminals, the collector of said PNP transistor of said selective input means being connected to the write terminal of said memory cell, the collector of said NPN transistor of said selective input means being connected to the emitter of said NPN transistor of said read-out means.
Claim 6
Dependent Claim
191 words
A memory circuit comprising a memory cell of PNPN- equivalent 4-layer construction with a write terminal and a read terminal, selective input means composed of a pair of an NPN transistor and a PNP transistor, and read-out means including a PNP transistor and an NPN transistor, the collector of said PNP transistor of said read-out means being connected to a read output terminal, the base of said PNP transistor of said read-out means being connected to the collector of said NPN transistor of said read-out means, the base of said NPN transistor of said read-out means being connected to the read terminal of said memory cell, the emitters of said transistors of said selective input means being connected to one of two selective input terminals, the bases of said transistors of said selective input means being connected to the other of said two selective input terminals, the collector of said PNP transistor of said selective input means being connected to the write terminal of said memory cell, the collector of said NPN transistor of said selective input means being connected to the emitter of said NPN transistor of said read-out means.
Claim 7
Dependent Claim
55 words
A memory circuit according to claim 1, in which said memory cell consists of a composite circuit including a PNP transistor and an NPN transistor, the base of said PNP transistor being connected to the collector of said NPN transistor, the base of said NPN transistor being connected to the collector of said PNP transistor.
Claim 8
Dependent Claim
55 words
A memory circuit according to claim 2, in which said memory cell consists of a composite circuit including a PNP transistor and an NPN transistor, the base of said PNP transistor being connected to the collector of said NPN transistor, the base of said NPN transistor being connected to the collector of said PNP transistor.
Claim 9
Dependent Claim
55 words
A memory circuit according to claim 3, in which said memory cell consists of a composite circuit including a PNP transistor and an NPN transistor, the base of said PNP transistor being connected to the collector of said NPN transistor, the base of said NPN transistor being connected to the collector of said PNP transistor.
Claim 10
Dependent Claim
89 words
A memory circuit according to claim 2, in which said memory cell consists of a composite circuit including a PNP transistor of multi-emitter construction and an NPN transistor, the base of said PNP transistor being connected to the collector of said NPN transistor, the base of said NPN transistor being connected to the collector of said PNP transistor, one of the emitters of said PNP transistor being used as the read terminal of the memory cell and connected to the base of said PNP transistor of said read-out means.
Claim 11
Dependent Claim
89 words
A memory circuit according to claim 3, in which said memory cell consists of a composite circuit including a PNP transistor and an NPN transistor of multi-emitter construction, the base of said PNP transistor being connected to the collector of said NPN transistor, the base of said NPN transistor being connected to the collector of said PNP transistor, one of the emitters of said NPN transistor being used as the read terminal of the memory cell and connected to the base of said NPN transistor of said read-out means.
Claim 12
Dependent Claim
89 words
A memory circuit according to claim 3, in which said memory cell consists of a composite circuit including a PNP transistor of multi-collector construction and an NPN transistor, the base of said PNP transistor being connected to the collector of said NPN transistor, the base of said NPN transistor being connected to the collector of said PNP transistor, one of two collectors of said PNP transistor being used as the read terminal of the memory cell and connected to the base of said NPN transistor of said read-out means.
References Cited (Backward Citations)
US3986177A
Cited
US3918033A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-02 | 1981-07-04 | 1982-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-02 | 1985-07-04 | 1986-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-02 | 1989-07-04 | 1990-01-03 | $7700.00 | Window Closed / Lapsed |