US4064483A — Error correcting circuit arrangement using cube c…

Claim 1

Independent Claim 212 words

Error correcting circuit utilizing a cube circuit for correcting errors in the data (d 0 d 1 d 2 . . . d n ) having n+1 bits in accordance with the syndromes S 1 and S 3 , ##EQU11## which are obtainable from the calculation of a check matrix H for the BCH code ##EQU12## said error correcting circuit comprising: generator means for generating said syndromes S 1 and S 3 based on the check matrix H; means for providing a term (S 1 - a i ) based on the modulo 2 calculation to the i th line vector ##EQU13## of said check matrix H corresponding to each data bit d i ; means for multiplying said (S 1 - a i ) term by three times so as to cube said term; means for providing a term (S 3 - a i 3 ) based on the modulo 2 calculation to the i th line vector ##EQU14## of said check matrix H corresponding to each data bit d i ; check means for checking the accordance between the terms (S 1 - a i ) 3 -- and (S 3 - a i 3 ); and inverting means for inverting said d i bit when the accordance is detected.

Claim 2

Dependent Claim 212 words

Error correcting circuit utilizing a cube circuit for correcting errors in the data (d 0 d 1 d 2 . . . d n ) having n+1 bits in accordance with the syndromes S 1 and S 3 , ##EQU11## which are obtainable from the calculation of a check matrix H for the BCH code ##EQU12## said error correcting circuit comprising: generator means for generating said syndromes S 1 and S 3 based on the check matrix H; means for providing a term (S 1 - a i ) based on the modulo 2 calculation to the i th line vector ##EQU13## of said check matrix H corresponding to each data bit d i ; means for multiplying said (S 1 - a i ) term by three times so as to cube said term; means for providing a term (S 3 - a i 3 ) based on the modulo 2 calculation to the i th line vector ##EQU14## of said check matrix H corresponding to each data bit d i ; check means for checking the accordance between the terms (S 1 - a i ) 3 -- and (S 3 - a i 3 ); and inverting means for inverting said d i bit when the accordance is detected.

Claim 3

Dependent Claim 129 words

Error correcting circuit as set forth in claim 1, wherein said respective means for providing said (S 1 - a i ) and (S 3 - a i 3 ) terms comprise a plurality of signal lines for producing syndromes S 1 and S 1 , and a plurality of signal lines for producing syndromes S 3 and S 3 , respectively, and a plurality of output lines selectively connected to the S 1 and S 1 signal lines in accordance with each value a i among said S 1 and S 1 signal lines, and a plurality of output lines selectively connected to the S 3 and S 3 signal lines in accordance with each value a i among said S 3 and S 3 signal lines, respectively.

Claim 4

Dependent Claim 39 words

Error correcting circuit as set forth in claim 1, wherein said error correcting circuit comprises a parallel arrangement of individual multiplying means, providing means, check means and inverting means, one of each for each data bit d i .

Claim 5

Dependent Claim 187 words

Error correcting circuit utilizing a cube circuit for correcting errors in the data (d 0 d 1 d 2 . . . d n ) having n+1 bits in accordance with the syndrome S 1 and S 3 , where ##EQU15## which are obtainable from calculation of the check matrix H for a BCH code, said error correcting circuit comprising: a read only memory for storing a conversion table for converting (S 1 - a i ) = (A 0 A 1 A 2 A 3 A 4 A 5 ) to (S 1 - a i ) 3 = (B 0 B 1 B 2 B 3 B 4 B 5 ), means responsive to a given value of (S 1 - a i ) for addressing said read only memory to cause readout of a corresponding value of (S 1 - a i ) 3 , check means for checking the coincidence between the values of (S 1 - a i ) 3 and (S 3 - a i 3 ), and inverting means for inverting said d i bit when the coincidence is detected.

Claim 6

Dependent Claim 187 words

Error correcting circuit utilizing a cube circuit for correcting errors in the data (d 0 d 1 d 2 . . . d n ) having n+1 bits in accordance with the syndrome S 1 and S 3 , where ##EQU15## which are obtainable from calculation of the check matrix H for a BCH code, said error correcting circuit comprising: a read only memory for storing a conversion table for converting (S 1 - a i ) = (A 0 A 1 A 2 A 3 A 4 A 5 ) to (S 1 - a i ) 3 = (B 0 B 1 B 2 B 3 B 4 B 5 ), means responsive to a given value of (S 1 - a i ) for addressing said read only memory to cause readout of a corresponding value of (S 1 - a i ) 3 , check means for checking the coincidence between the values of (S 1 - a i ) 3 and (S 3 - a i 3 ), and inverting means for inverting said d i bit when the coincidence is detected.

Claim 7

Dependent Claim 207 words

Error correcting circuit for correcting errors in the data (d 0 d 1 d 2 . . . d n ) having n+1 bits in accordance with the syndromes S 1 and S 3 , ##EQU16## which are obtainable from the calculation of a check matrix H for the BCH code ##EQU17## said error correcting circuit comprising: means for generating said syndromes S 1 and S 3 from the check matrix H; means for providing a term (S 1 - a i ) based on the modulo 2 calculation to the i th line vector ##EQU18## of said check matrix H corresponding to each data bit d i ; means for cubing said (S 1 - a i ) term to provide (S 1 - a i ) 3 ; means for providing a term (S 3 - a i 3 ) based on the modulo 2 calculation to the i th line vector ##EQU19## of said check matrix H corresponding to each data bit d i ; means for detecting coincidence between (S 1 - a i ) 3 and (S 3 - a i 3 ); and means responsive to said coincidence detected by said detecting means for correcting said data bit d i .

Claim 8

Dependent Claim 207 words

Error correcting circuit for correcting errors in the data (d 0 d 1 d 2 . . . d n ) having n+1 bits in accordance with the syndromes S 1 and S 3 , ##EQU16## which are obtainable from the calculation of a check matrix H for the BCH code ##EQU17## said error correcting circuit comprising: means for generating said syndromes S 1 and S 3 from the check matrix H; means for providing a term (S 1 - a i ) based on the modulo 2 calculation to the i th line vector ##EQU18## of said check matrix H corresponding to each data bit d i ; means for cubing said (S 1 - a i ) term to provide (S 1 - a i ) 3 ; means for providing a term (S 3 - a i 3 ) based on the modulo 2 calculation to the i th line vector ##EQU19## of said check matrix H corresponding to each data bit d i ; means for detecting coincidence between (S 1 - a i ) 3 and (S 3 - a i 3 ); and means responsive to said coincidence detected by said detecting means for correcting said data bit d i .

Claim 9

Dependent Claim 30 words

Error correcting circuit as set forth in claim 5, wherein said cubing means is a multiplier circuit for multiplying said (S 1 - a i ) term by itself twice.

Claim 10

Dependent Claim 73 words

Error correcting circuit as set forth in claim 5, wherein said cubing means comprises a read only memory for holding a table for converting any term (S 1 - x) to (S 1 - x) 3 , and means responsive to a given value of said (S 1 - a i ) term for addressing said memory so as to read out a value of (S 1 - a i ) 3 .

Claim 11

Dependent Claim 52 words

Error correcting circuit as set forth in claim 5, wherein there are a plurality of (S 1 - a i ) term providing means, cubing means, (S 3 - a i 3 ) term providing means, detecting means and correcting means, one for each data bit d i , arranged in parallel.

Claim 12

Dependent Claim 48 words

Error correcting circuit as set forth in claim 8, wherein said individual (S 1 - a i ) term providing means, cubing means, (S 3 - a i 3 ) term providing means, detecting means and correcting means are implemented by individual integrated circuits of identical circuit design.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1980-12-19	1981-06-20	1981-12-20	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1984-12-19	1985-06-20	1985-12-20	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1988-12-19	1989-06-20	1989-12-20	$7700.00	Window Closed / Lapsed

Error correcting circuit arrangement using cube circuits

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