Fundamental logic circuit

Claim 2

A logic circuit comprising: a semiconductor layer having a terminal for receiving a supply potential; and a plurality of circuit elements carried by said semiconductor layer defining a multiple gate field effect transistor the gates of which represent the logic inputs of said logic circuit, and a multiple emitter bipolar transistor integrated with said field effect transistor, at least one of the emitters representing the output of said logic circuit.

Claim 3

A logic circuit according to claim 1, wherein said plurality of circuit elements further define another field effect transistor having a gate connected to another of the emitters of said multiple emitter bipolar transistor, and a source-drain path connected between said other emitter and a reference potential.

Claim 4

A logic circuit comprising: a doped semiconductor layer; a terminal carried by said layer for receiving a first voltage supply potential; first and second zones doped oppositely to said semiconductor layer and spaced apart therein to have a channel zone therebetween and define a source and drain, respectively, of a MOS field effect transistor; an insulating layer carried by said semiconductor layer over the channel zone between said source and drain; a plurality of gate electrodes for the MOS field effect transistor carried on said insulating layer insulated from each other and arranged in a pattern in which each covers a respective portion of the channel zone such that application of a voltage which is effective to form the channel requires application of the suitable voltage to at least one of said gate electrodes, said plurality of electrodes constituting the logic inputs of said logic circuit; third and fourth zones doped oppositely to said second zone and spaced apart therein, said zone also constituting a base and said third and fourth zones consituting emitters and said semiconductor layer constituting the collector of a bipolar transistor, at least one of said emitters constituting an output for said logic circuit; and a load element in said semiconductor layer connected to said output and including a terminal for receiving a second voltage supply potential.

Claim 5

A logic circuit comprising: a doped semiconductor layer; a terminal carried by said layer for receiving a first voltage supply potential; first and second zones doped oppositely to said semiconductor layer and spaced apart therein to have a channel zone therebetween and define a source and drain, respectively, of a MOS field effect transistor; an insulating layer carried by said semiconductor layer over the channel zone between said source and drain; a plurality of gate electrodes for the MOS field effect transistor carried on said insulating layer insulated from each other and arranged in a pattern in which each covers a respective portion of the channel zone such that application of a voltage which is effective to form the channel requires application of the suitable voltage to at least one of said gate electrodes, said plurality of electrodes constituting the logic inputs of said logic circuit; third and fourth zones doped oppositely to said second zone and spaced apart therein, said zone also constituting a base and said third and fourth zones consituting emitters and said semiconductor layer constituting the collector of a bipolar transistor, at least one of said emitters constituting an output for said logic circuit; and a load element in said semiconductor layer connected to said output and including a terminal for receiving a second voltage supply potential.

Claim 6

The logic circuit of claim 3, wherein said plurality of gate electrodes comprises a pair of gate electrodes each extending the length of the channel zone across the spacing between said first and second doped zones so that the application of said suitable voltage to either of the electrodes will effect channel formation of said logic circuit thereby operates as a NAND circuit.

Claim 7

The logic circuit of claim 3, wherein said load element is in the form of a MOS transistor comprising: fifth and sixth zones doped oppositely to the semiconductor layer and spaced apart therein as a source and a drain, respectively, said source connected to said output emittter and said drain carrying said terminal which receives the second voltage supply potential; another insulating layer carried on said semiconductor layer between said fifth and sixth zones; and another gate carried on the last-mentioned insulating layer and connected to said output emitter.

Claim 8

The logic circuit of claim 3, comprising: a further bipolar transistor including a collector constituted by said semiconductor layer, a fifth zone in and doped oppositely to said semiconductor layer constituting a base and electrically connected to one of said emitters of the multiple emitter first-mentioned bipolar transistor, and a sixth zone in and doped oppositely to said fifth zone constituting an emitter, said further bipolar transistor represented a Darlington stage.

Claim 9

The logic circuit of claim 3, comprising: another logic circuit integrated in said semiconductor layer and connected in common to said load element.

Claim 10

The logic circuit of claim 3, comprising: a buried layer carrying said semiconductor layer, said buried layer doped with the same conductivity as and to a greater degree than said semiconductor layer.

Claim 11

The logic circuit of claim 3, wherein each of said gate electrodes extends over a portion of the distance between said first and second doped zones such that all of said gate electrodes receive the suitable voltage to effect channel formation and said logic circuit thereby operates as a NOR circuit.

Claim 12

The logic circuit of claim 9, comprising: ion implanted charge carriers in said semiconductor layer beneath the spaces between said gate electrodes to avoid potential barriers between the gate electrodes.

Claim 13

The logic circuit of claim 9, wherein said gate electrodes are constructed in Si-Al technique to avoid potential barriers between the gate electrodes.

Claim 14

A logic circuit comprising: an n-doped semiconductor layer; a terminal carried by said layer for receiving a first voltage supply potential; first and second p-doped zones spaced apart in said semiconductor layer and having a channel zone therebetween and define a source and drain, respectively, of a MOS field effect transistor; an insulating layer carried by said semiconductor layer over the channel zone between said source and drain; a plurality of gate electrodes for the MOS field effect transistor carried on said insulating layer insulated from each other and arranged in a pattern in which each covers a respective portion of the channel zone such that application of a voltage which is effective to form the channel requires application of the suitable voltage to at least one of said gate electrodes, said plurality of electrodes constituting the logic inputs of said logic circuit; third and fourth n-doped zones spaced apart in said second zone, said second zone also constituting a base and said third and fourth zones constituting emitters and said semiconductor layer constituting the collector of a bipolar transistor, at least one of said emitters constituting an output for said logic circuit; and a load element in said semiconductor layer connected to said output and including a terminal for receiving a second voltage supply potential.

Claim 15

A logic circuit comprising: an n-doped semiconductor layer; a terminal carried by said layer for receiving a first voltage supply potential; first and second p-doped zones spaced apart in said semiconductor layer and having a channel zone therebetween and define a source and drain, respectively, of a MOS field effect transistor; an insulating layer carried by said semiconductor layer over the channel zone between said source and drain; a plurality of gate electrodes for the MOS field effect transistor carried on said insulating layer insulated from each other and arranged in a pattern in which each covers a respective portion of the channel zone such that application of a voltage which is effective to form the channel requires application of the suitable voltage to at least one of said gate electrodes, said plurality of electrodes constituting the logic inputs of said logic circuit; third and fourth n-doped zones spaced apart in said second zone, said second zone also constituting a base and said third and fourth zones constituting emitters and said semiconductor layer constituting the collector of a bipolar transistor, at least one of said emitters constituting an output for said logic circuit; and a load element in said semiconductor layer connected to said output and including a terminal for receiving a second voltage supply potential.

Claim 16

A logic circuit comprising: a p-doped semiconductor layer; a terminal carried by said layer for receiving a first voltage supply potential; first and second n-doped zones spaced apart in said semiconductor layer and having a channel zone therebetween and define a source and drain, respectively, of a MOS field effect transistor; an insulating layer carried by said semiconductor layer over the channel zone between said source and drain; a plurality of gate electrodes for the MOS field effect transistor carried on said insulating layer insulated from each other and arranged in a pattern in which each covers a respective portion of the channel zone such that application of a voltage which is effective to form the channel requires application of the suitable voltage to at least one of said gate electrodes, said plurality of electrodes constituting the logic inputs of said logic circuit; third and fourth p-doped zones spaced apart in said second zone, said second zone also constituting a base and said third and fourth zones constituting emitters and said semiconductor layer constituting the collector of a bipolar transistor, at least one of said emitters constituting an output for said logic circuit; and a load element in said semiconductor layer connected to said output and including a terminal for receiving a second voltage supply potential.

Claim 17

A logic circuit comprising: a p-doped semiconductor layer; a terminal carried by said layer for receiving a first voltage supply potential; first and second n-doped zones spaced apart in said semiconductor layer and having a channel zone therebetween and define a source and drain, respectively, of a MOS field effect transistor; an insulating layer carried by said semiconductor layer over the channel zone between said source and drain; a plurality of gate electrodes for the MOS field effect transistor carried on said insulating layer insulated from each other and arranged in a pattern in which each covers a respective portion of the channel zone such that application of a voltage which is effective to form the channel requires application of the suitable voltage to at least one of said gate electrodes, said plurality of electrodes constituting the logic inputs of said logic circuit; third and fourth p-doped zones spaced apart in said second zone, said second zone also constituting a base and said third and fourth zones constituting emitters and said semiconductor layer constituting the collector of a bipolar transistor, at least one of said emitters constituting an output for said logic circuit; and a load element in said semiconductor layer connected to said output and including a terminal for receiving a second voltage supply potential.