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US4063184A Expired / Lapsed US ⏱️ 0.0 years remaining

Signal transfer circuit

Assignee: Sony Corp
•
Filing: 1976-09-27
•
Granted: 1977-12-13
•
Expires: 1996-09-27
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Abstract

Abstract A signal transfer circuit suitable for a monolithic integrated circuit is operable to transfer only a desired DC biasing voltage and AC signal component from an FM discriminator output to a multiplex stereo demodulator circuit or the like at its rear stage, with a DC component contained in the FM discriminator output being cancelled and hence not transferred. The signal transfer circuit is composed of a parallel connection of a first loop including a first FM discriminating signal source and a first resistor connected in series to each other, and a second loop consisting of a second FM discriminating signal source providing an output signal which is of the same level but of reverse phase in respect to the output signal of the first discriminating signal source, second and third resistors connected in series to the second signal source, and an AC signal by-pass capacitor connected between a connection point between the second and third resistors and a reference point. A connection point of the above-mentioned parallel connection is connected to a DC biasing voltage source and the other connection point thereof is connected to an output terminal of the signal transfer circuit.

Inventors

  • 👤 Mitsuo Ohsawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 00:58
CPC Classifications
H; H04; H04H; H04H20/00; H04H20/86; H04H20/88; H03; H03D; H03D1/00; H03D1/22; H03D1/2209; H03D3/00; H03D3/001; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/1646; H04B1/26; H04B1/28; H04B3/00

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 147 words
A signal transfer circuit comprising: a first loop including a first signal source providing an output signal which is composed of an AC signal component superimposed on a DC voltage, and a first resistor connected in series with said first signal source; a second loop including a second signal source providing an output signal of substantially the same level as said output signal from the first signal source but of reversed polarity in respect to the latter, second and third resistors connected in series with said second signal source, and a capacitor connected between a reference point and a connection point of said second resistor with said third resistor; means connecting said first and second loops in parallel with each other at opposed connection points; and an output terminal connected with one of said connection points at which the first and second loops are connected in parallel.
Claim 2
Dependent Claim 147 words
A signal transfer circuit comprising: a first loop including a first signal source providing an output signal which is composed of an AC signal component superimposed on a DC voltage, and a first resistor connected in series with said first signal source; a second loop including a second signal source providing an output signal of substantially the same level as said output signal from the first signal source but of reversed polarity in respect to the latter, second and third resistors connected in series with said second signal source, and a capacitor connected between a reference point and a connection point of said second resistor with said third resistor; means connecting said first and second loops in parallel with each other at opposed connection points; and an output terminal connected with one of said connection points at which the first and second loops are connected in parallel.
Claim 3
Dependent Claim 33 words
A signal transfer circuit according to claim 1; in which said first resistor has a resistance value substantially equal to the sum of the resistance values of said second and third resistors, respectively.
Claim 4
Dependent Claim 34 words
A signal transfer circuit according to claim 1; further comprising a DC biasing voltage source connected with the other of said connection points at which the first and second loops are connected in parallel.
Claim 5
Dependent Claim 21 words
A signal transfer circuit according to claim 1; in which said first and second signal sources are respective FM discriminator outputs.
Claim 6
Dependent Claim 18 words
A signal transfer circuit according to claim 1; in which said capacitor in said second loop is variable.
Claim 7
Dependent Claim 70 words
A signal transfer circuit according to claim 1; in which said first resistor has a resistance value substantially equal to the sum of the resistance values of said second and third resistors, respectively; a DC biasing voltage source is connected with the other of said connection points at which the first and second loop are connected in parallel; and said first and second signal sources are respective FM discriminator outputs.
Claim 8
Dependent Claim 18 words
A signal transfer circuit according to claim 6; in which said capacitor in the second loop is variable.

References Cited (Backward Citations)

US3493871A Cited
US3882405A Cited
US3947629A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-12-12 1981-06-13 1981-12-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-12-12 1985-06-13 1985-12-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-12-12 1989-06-13 1989-12-13 $7700.00 Window Closed / Lapsed

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