High performance analog to digital converter for integrated circuits

Claim 2

An analog to digital converter for converting an unknown analog input voltage into a digital equivalent thereof including a calibration means comprising: a. storage means, b. means for applying said input voltage to said storage means, c. means for altering the charge held by said storage means by discrete equal amounts in response to control pulses applied to said means for altering, d. means for applying control pulses to said means for altering, e. threshold means connected to said storage means for detecting when the charge on said storage means reaches a predetermined threshold value, f. accumulator means responsive to the said control pulses for accumulating a number of corresponding to the voltage applied to said storage means, g. means for applying a reference voltage to said storage means the resulting charge held by said storage means means again being altered in discrete equal amounts by said means for altering, and h. means, responsive to said threshold means and said accumulator means and connected to said means for altering, for comparing the time of detection of said predetermined threshold by said threshold means with a known time corresponding to a number of control pulses nominally required for varying the charge held by said storage means from its initial value when said reference voltage is applied thereto to a value corresponding to said predetermined threshold value, and for varying said discrete amount in accordance with the difference between said time of detection and said known time.

Claim 3

An analog to digital converter for converting an unknown analog input voltage into a digital equivalent thereof including a calibration means comprising: a. a storage means, b. means for applying said input voltage to said storage means, c. a voltage controlled constant current source for constantly drawing a current of a magnitude dependent upon a voltage applied at a control input thereof, d. means for altering the charge held by said storage means by discrete equal amounts in response to control pulses applied thereto by connecting said voltage controlled constant current source to said storage means during the presence of each control pulse to cause said constant current to flow through said storage means and alter the charge held by said storage means said discrete amount which is dependent upon the magnitude of said constant current, e. means for applying control pulses to said means for altering, f. threshold means connected to said storage means for detecting when the charge on said storage means reaches a predetermined threshold value, g. accumulator means responsive to the said control pulses for accumulating a number corresponding to the voltage applied to said storage means, h. means for applying a reference voltage to said storage means, the resulting charge held by said storage means again being altered in discrete equal amounts by said means for altering, and i. means, responsive to said threshold means and connected to said means for altering, for comparing the time of detection of said predetermined threshold by said threshold means with a known time corresponding to a number of control pulses nominally required for varying the charge held by said storage means from its initial value when said reference voltage is applied thereto to a value corresponding to said predetermined threshold value, and for varying said discrete amount in accordance with the difference between said time of detection and said known time.

Claim 4

An analog to digital converter for converting an unknown analog input voltage into a digital equivalent thereof including a calibration means comprising: a. a storage means, b. means for applying said input voltage to said storage means, c. a voltage controlled constant current source for constantly drawing a current of a magnitude dependent upon a voltage applied at a control input thereof, d. means for altering the charge held by said storage means by discrete equal amounts in response to control pulses applied thereto by connecting said voltage controlled constant current source to said storage means during the presence of each control pulse to cause said constant current to flow through said storage means and alter the charge held by said storage means said discrete amount which is dependent upon the magnitude of said constant current, e. means for applying control pulses to said means for altering, f. threshold means connected to said storage means for detecting when the charge on said storage means reaches a predetermined threshold value, g. accumulator means responsive to the said control pulses for accumulating a number corresponding to the voltage applied to said storage means, h. means for applying a reference voltage to said storage means, the resulting charge held by said storage means again being altered in discrete equal amounts by said means for altering, and i. means, responsive to said threshold means and connected to said means for altering, for comparing the time of detection of said predetermined threshold by said threshold means with a known time corresponding to a number of control pulses nominally required for varying the charge held by said storage means from its initial value when said reference voltage is applied thereto to a value corresponding to said predetermined threshold value, and for varying said discrete amount in accordance with the difference between said time of detection and said known time.

Claim 5

The analog to digital converter as claimed in claim 2 wherein said means for comparing and for varying comprises: a. a phase discriminator means having first and second input terminals and responsive to the time difference of arrival of signals at said first and second input terminals for generating an output voltage of a polarity and magnitude dependent upon the said time difference of arrival, and b. means connected to the voltage control terminal of said constant current source and the output of said phase discriminator, and having a control input terminal, for varying the voltage applied to said voltage control terminal of said constant current source in accordance with said phase discriminator output voltage when a control signal is applied to said control input terminal, and for holding constant the voltage applied to said voltage control terminal of said constant current source when said control signal is not applied to said control terminal.

Claim 6

The analog to digital converter as claimed in claim 3 wherein said threshold means provides an output signal IN 1 when said threshold means detects said predetermined threshold value, and further comprising means responsive to said control pulses, during the charge alteration caused by said control pulses being applied to said means for altering, for providing an output signal IN 2 after a predetermined number of said control pulses have been applied, said output signals IN 1 and IN 2 being connected, respectively, to said first and second input terminals of said phase discriminating means, wherein said predetermined number of control pulses is equal to the number of discrete amounts of charge alterations nominally required to alter the charge held by said storage means between a first value thereon immediately after application of said reference voltage, and said threshold value, and wherein the time of generation of said predetermined number of control pulses is said known time.

Claim 7

The analog to digital converter as claimed in claim 4 wherein said means for connecting said voltage controlled constant current source to said storage means comprises: a. a first bipolar transistor having base, emitter, and collector electrodes, said first transistor being connected between said constant current source and said storage means via said emitter and collector electrodes, said base electrode being connected to a fixed voltage level, b. a second bipolar transistor having base, emitter, and collector electrodes, said second transistor being connected between a voltage terminal and said constant current source via said emitter and collector terminals, and c. means connecting said control pulses to the base of said second transistor, whereby the presence and absence of said control pulses causes said constant current to flow through said first and second transistors alternately when said means for connecting is not disabled.

Claim 8

The analog to digital converter as claimed in claim 5 further comprising means connected to said means for connecting to disable said latter means for the purpose of preventing said means for altering from altering the charge on said storage means while said input voltage V IN or said reference voltage is being applied to said storage means.

Claim 9

The analog to digital converter as claimed in claim 6 wherein said means to disable comprises a third bipolar transistor having base, emitter and collector electrodes, said third transistor being connected between said voltage controlled constant current source and a voltage terminal via its emitter and collector electrodes, and a connection to said base terminal adapted to receive a disabling input voltage, whereby a disabling input voltage applied to said connection turns on said third transistor thereby providing a current path for said constant current and preventing said constant current from flowing through said first transistor.

Claim 10

The analog to digital converter as claimed in claim 7 wherein said means responsive to said control pulses for providing an output signal IN 2 comprises a decoder means in combination with said accumulator means; said decoder means being adapted to provide said output IN 2 when said accumulator means accumulates said predetermined number of control pulses.

Claim 11

The analog to digital converter as claimed in claim 8 wherein said storage means is a capacitive storage element.

Claim 12

The analog to digital converter as claimed in claim 9 wherein said means for applying said input voltage V IN to said storage means is a first FET device having source drain and gate leads, said source and drain leads being connected between an input terminal which V IN is applied and said capacitive storage element, and said gate lead adapted to receive a gating input for turning on said first FET device.

Claim 13

The analog to digital converter as claimed in claim 10 wherein said means for applying a reference voltage to said storage means comprises a second FET device having source drain and gate leads, said source and drain leads being connected between a reference terminal to which said reference voltage is applied and said capacitive storage element, and said gate lead adapted to receive a gating input for turning on said second FET device.

Claim 14

The analog to digital converter as claimed in claim 9 wherein said means for applying said input voltage V IN to said storage means comprises: a. an input terminal adapted to receive said input voltage, b. an input bipolar transistor having base, emitter and collector electrodes, said emitter connected to said capacitive storage element, said collector connected to a voltage supply terminal, and c. a first FET device having source, drain and gate leads, said FET device being connected between said input terminal and said base electrode of said input bipolar transistor via said source and drain terminals, and said gate lead adapted to receive a gating input for turning on said first FET device.

Claim 15

The analog to digital converter as claimed in claim 12 wherein said means for applying a reference voltage to said storage means comprises: a. a second input terminal adapted to receive said reference voltage, and b. a second FET device having source, drain and gate electrodes, said second FET device being connected between said second input terminal and the base electrode of said input bipolar transistor via its source and drain leads, and said gate lead adapted to receive a gating input for turning on said second FET device.

Claim 16

The analog to digital converter as claimed in claim 13 further comprising means for applying to said capacitive storage element a voltage equal to the forward base-emitter voltage drop of said input bipolar transistor.

Claim 17

The analog to digital converter as claimed in claim 14 wherein said last mentioned means comprises: a. a high gain negative feedback circuit connected between said capacitive storage element and one of said input and second input terminals, b. switch means for enabling and disabling said feedback circuit, and c. a third FET device having drain, source and gate leads, said third FET being connected between said one terminal and said capacitive storage element, and said gate leads adapted to receive a gating input for turning on said third FET device.