US4058807A
Expired / Lapsed
US
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Digital antilogarithmic converter circuit
Assignee: Nidec Precision Corp
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Filing: 1976-04-15
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Granted: 1977-11-15
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Expires: 1996-04-15
Abstract
Abstract A digital antilogarithmic converter circuit converts digitally logarithmically converted digital information to its antilogarithm. The digital information to be converted is separated into the number to the right of the decimal point and the number to the left of the decimal point. The number less than the decimal point is digitally converted to a linear approximation of its antilogarithm. The number more than decimal point is digitally converted to its antilogarithm. Said linear approximation of the antilogarithm of the number less than the decimal point is digitally multiplied by said antilogarithm of the number more than the decimal point to obtain the antilogarithm of said digital information.
Inventors
- 👤 Masaru Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:18
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/556; G01; G01J; G01J1/00; G01J1/42; G01J1/44
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
184 words
A circuit for receiving logarithmically converted digital information and producing a signal having a period in reverse proportion to an antilogarithmic value of said digital information comprising: a counter for counting a clock pulse of a predetermined frequency to provide various divided frequencies; a data selector for receiving the number more than decimal point of the digital input information and selecting a particular one of the various divided frequencies from said counter in accordance with the received number; a divider for dividing the selected frequency from said selector to provide a signal having a period related to the antilogarithmic value of the number more than the decimal point of the input information; an AND circuit having two inputs connected to the input and output of said divider, respectively; and a presettable counter which is presetted to the number less than the decimal point of the input information by a start signal and for then receiving as clock pulses the output pulses from said AND circuit to produce an output signal having a period in reverse proportion to the antilogarithmic value of the input information.
Claim 2
Dependent Claim
184 words
A circuit for receiving logarithmically converted digital information and producing a signal having a period in reverse proportion to an antilogarithmic value of said digital information comprising: a counter for counting a clock pulse of a predetermined frequency to provide various divided frequencies; a data selector for receiving the number more than decimal point of the digital input information and selecting a particular one of the various divided frequencies from said counter in accordance with the received number; a divider for dividing the selected frequency from said selector to provide a signal having a period related to the antilogarithmic value of the number more than the decimal point of the input information; an AND circuit having two inputs connected to the input and output of said divider, respectively; and a presettable counter which is presetted to the number less than the decimal point of the input information by a start signal and for then receiving as clock pulses the output pulses from said AND circuit to produce an output signal having a period in reverse proportion to the antilogarithmic value of the input information.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-11-14 | 1981-05-16 | 1981-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-11-14 | 1985-05-16 | 1985-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-11-14 | 1989-05-16 | 1989-11-15 | $7700.00 | Window Closed / Lapsed |