US4056846A
Expired / Lapsed
US
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Data processing system with apparatus for sharing channel background processing
Assignee: International Business Machines Corp
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Filing: 1976-06-30
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Granted: 1977-11-01
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Expires: 1996-06-30
Abstract
Abstract In a data processing system having a plurality of channels that are organized for separately processing the operations of specific I/O devices and the operations that are background to these specific operations, apparatus for transferring the background processing from one channel to another channel to distribute the background processing load. A system of registers and lines connect these registers to the channels for controlling these operations. Each channel processor has a request register for use in designating that background processing has been completed and that processing of a device oriented portion of a channel program is to begin, and a completion register set by an associated I/O processor for use in signifying that processing of a device oriented portion of a channel program has been completed and that background processing is to begin.
Inventors
- 👤 Robert William Callahan
- 👤 Paul Eugene Kauffman
- 👤 Lawrence Joseph Kobesky
- 👤 Howard Loomis Page
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:05
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
309 words
In a data processing system having a plurality of I/O processors each having a time slice operation with a plurality of time slices for executing portions of channel programs oriented to a particular I/O device for each time slice and one time slice for executing background portions of all channel programs, the improvement comprising, means connecting each of said I/O processors to receive an attention signal from a central processor for beginning processing by the background time slice of any I/O device, each of said I/O processors having a first register having a bit position for each device oriented time slice of the associated I/O processor, means connecting the input of said first register to each of said I/O processors to be set by a background time slice in a bit position identifying one of the device oriented time slices for which background processing has been completed by any background time slice, means connecting the output of said first register to the associated I/O processor to identify the device oriented time slice for which the background processing has been completed, means connecting the input of said first register to the associated I/O processor to be reset when a device oriented resource has responded to the output of said first register, a second register for each I/O processor having a bit position for each device oriented time slice of the associated I/O processor, means connecting said second register to be set by a device oriented time slice of the associated I/O processor when device oriented processing has been completed, means connecting the output of said second register to each I/O processor to signal any background time slice that background processing is required by a particular device oriented time slice of the I/O processor and, means connecting the input of said second register to be reset by any background time slice.
Claim 2
Dependent Claim
309 words
In a data processing system having a plurality of I/O processors each having a time slice operation with a plurality of time slices for executing portions of channel programs oriented to a particular I/O device for each time slice and one time slice for executing background portions of all channel programs, the improvement comprising, means connecting each of said I/O processors to receive an attention signal from a central processor for beginning processing by the background time slice of any I/O device, each of said I/O processors having a first register having a bit position for each device oriented time slice of the associated I/O processor, means connecting the input of said first register to each of said I/O processors to be set by a background time slice in a bit position identifying one of the device oriented time slices for which background processing has been completed by any background time slice, means connecting the output of said first register to the associated I/O processor to identify the device oriented time slice for which the background processing has been completed, means connecting the input of said first register to the associated I/O processor to be reset when a device oriented resource has responded to the output of said first register, a second register for each I/O processor having a bit position for each device oriented time slice of the associated I/O processor, means connecting said second register to be set by a device oriented time slice of the associated I/O processor when device oriented processing has been completed, means connecting the output of said second register to each I/O processor to signal any background time slice that background processing is required by a particular device oriented time slice of the I/O processor and, means connecting the input of said second register to be reset by any background time slice.
Claim 3
Dependent Claim
254 words
In a data processing system having a plurality of I/O processors and having a plurality of I/O devices each associated with a predetermined one of said I/O processors, said I/O processors each having concurrently operable resources for executing portions of channel programs oriented to particular I/O devices and for executing background portions of channel programs, the improvement comprising, means connecting each of said I/O processors to receive an attention signal from a central processor system signifying that background processing is to be performd by any available I/O processor for a channel program for a selected I/O device, a first register for each of said I/O processors having an input and an output and having a bit position for each of said concurrently operable resources for device oriented portions of channel programs of the associated I/O processor, means connecting the input of said first register to each of said I/O processors for setting a bit position identifying one of said device oriented resources for which background processing has been completed by any of said I/O processors, means connecting the output of said first register to the associated I/O processor to identify the device oriented resource for which the background processing has been completed, and a second register for each of said I/O processors having an input and an output and means connecting said second register with each I/O processor to signal every I/O processor that device oriented processing has been completed and that further background processing is to be performed by any available I/O processor.
Claim 4
Dependent Claim
254 words
In a data processing system having a plurality of I/O processors and having a plurality of I/O devices each associated with a predetermined one of said I/O processors, said I/O processors each having concurrently operable resources for executing portions of channel programs oriented to particular I/O devices and for executing background portions of channel programs, the improvement comprising, means connecting each of said I/O processors to receive an attention signal from a central processor system signifying that background processing is to be performd by any available I/O processor for a channel program for a selected I/O device, a first register for each of said I/O processors having an input and an output and having a bit position for each of said concurrently operable resources for device oriented portions of channel programs of the associated I/O processor, means connecting the input of said first register to each of said I/O processors for setting a bit position identifying one of said device oriented resources for which background processing has been completed by any of said I/O processors, means connecting the output of said first register to the associated I/O processor to identify the device oriented resource for which the background processing has been completed, and a second register for each of said I/O processors having an input and an output and means connecting said second register with each I/O processor to signal every I/O processor that device oriented processing has been completed and that further background processing is to be performed by any available I/O processor.
Claim 5
Dependent Claim
39 words
The data processing system of claim 2 wherein said first means includes means connecting the input of said first register to the associated I/O processor to be reset when a device oriented resource has responded to the output signal.
Claim 6
Dependent Claim
116 words
The data processing system of claim 3 wherein said second means comprises, a second register for each I/O processor having a bit position for each of said concurrently operable device oriented resources of the associated I/O processor and having an input and an output, means connecting the input of said second register to be set by the associated I/O processor when device oriented processing has been completed, means connecting the output of said second register to each I/O processor to signal that background processing is required by a channel program associated with a particular resource of the I/O processor, and, means connecting the input of said second register to be reset by a background processing resource.
References Cited (Backward Citations)
US3702462A
Cited
US3801962A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-31 | 1981-05-02 | 1981-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-31 | 1985-05-02 | 1985-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-31 | 1989-05-02 | 1989-11-01 | $7700.00 | Window Closed / Lapsed |