US4054903A
Expired / Lapsed
US
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Video time base corrector
Assignee: Sony Corp
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Filing: 1976-07-08
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Granted: 1977-10-18
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Expires: 1996-07-08
Abstract
Abstract In a time base corrector which converts incoming video signals to digital form and writes the digitized signals in sequentially enabled units of a main memory at a clocking rate varying generally in accordance with time base errors in the incoming signals, whereupon the signals temporarily stored in the memory are read out or fetched from the successive main memory units at a standard clocking rate and reconverted to analog form for eliminating the time base errors: a drop-out memory stores drop-out information in respect to drop-outs detected in the incoming video signals written in each of the main memory units; drop-outs are eliminated in the output from the time base corrector by rewriting, in each memory unit storing video signals having drop-out as indicated by the drop-out memory, video signals from another memory unit shown by the drop-out memory to be free of drop-out, with such rewriting being effected simultaneously with the read out of the video signals from such other memory unit; and upon the rewriting of video signals in a memory unit, the stored drop-out indicating information in respect to that memory unit is erased from the drop-out memory. Further, the clocking rate for reading out the video signals from each of the main memory units is modulated in accordance with velocity error information stored in a velocity error memory during writing of such video signals in the respective main memory unit, and the velocity error memory is operative, upon rewriting in a main memory unit for eliminating drop-out, to replace the velocity error information stored in respect to such main memory unit with the velocity error information associated with the main memory unit from which the rewritten video signals are drawn.
Inventors
- 👤 Takeshi Ninomiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:34
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/87; H04N9/88; H04N9/882; H04N9/885; H04N9/89; H04N9/896
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
368 words
A time base corrector for removing time base errors from video signals comprising: main memory means including a plurality of memory units each having a capacity sufficient to store a predetermined whole number of line intervals of the video signals; input means for receiving the video signals; write clock generating means coupled to said input means for generating write clock pulses at a variable rate dependent upon time base errors in the incoming video signals; read clock generating means for generating read clock pulses at a rate which is standard at least at the beginning and end of each standard line interval of the video signals; main memory control means for selectively enabling said memory units to write therein the video signals received from said input means at a clocking rate determined by said write clock pulses, and for selectively enabling said memory units to read out therefrom, at a clocking rate determined by said read clock pulses, the video signals written in said memory units; output means for receiving the video signals selectively read out from said memory units; drop-out detecting means for providing drop-out information in respect to the video signals received by said input means; drop-out memory means having a plurality of addresses respectively corresponding to said memory units for storing said drop-out information in respect to the video signals written in the respective memory units; and system control means including write addressing means generating write addresses of said memory units in a repeating cyclic order for causing said main memory control means to selectively enable said memory units in said repeating cyclic order for the writing therein of the video signals received from said input means, and read addressing means responsive to the drop-out information stored in said drop-out memory means for generating read addresses causing said main memory control means to selectively enable the thereby read addressed memory units for the reading-out of the video signals stored therein, with each memory unit thus addressed for reading-out being different from the memory unit then addressed for writing and further being a memory unit storing video signals free of drop-out as indicated by the drop-out information at the respective address in said drop-out memory means.
Claim 2
Dependent Claim
368 words
A time base corrector for removing time base errors from video signals comprising: main memory means including a plurality of memory units each having a capacity sufficient to store a predetermined whole number of line intervals of the video signals; input means for receiving the video signals; write clock generating means coupled to said input means for generating write clock pulses at a variable rate dependent upon time base errors in the incoming video signals; read clock generating means for generating read clock pulses at a rate which is standard at least at the beginning and end of each standard line interval of the video signals; main memory control means for selectively enabling said memory units to write therein the video signals received from said input means at a clocking rate determined by said write clock pulses, and for selectively enabling said memory units to read out therefrom, at a clocking rate determined by said read clock pulses, the video signals written in said memory units; output means for receiving the video signals selectively read out from said memory units; drop-out detecting means for providing drop-out information in respect to the video signals received by said input means; drop-out memory means having a plurality of addresses respectively corresponding to said memory units for storing said drop-out information in respect to the video signals written in the respective memory units; and system control means including write addressing means generating write addresses of said memory units in a repeating cyclic order for causing said main memory control means to selectively enable said memory units in said repeating cyclic order for the writing therein of the video signals received from said input means, and read addressing means responsive to the drop-out information stored in said drop-out memory means for generating read addresses causing said main memory control means to selectively enable the thereby read addressed memory units for the reading-out of the video signals stored therein, with each memory unit thus addressed for reading-out being different from the memory unit then addressed for writing and further being a memory unit storing video signals free of drop-out as indicated by the drop-out information at the respective address in said drop-out memory means.
Claim 3
Dependent Claim
135 words
A time base corrector according to claim 1; in which said main memory control means includes rewriting means for selectively rewriting, in any one of said memory units, video signals being read-out of any other one of said memory units; said system control means further includes means responsive to the drop-out information stored in said drop-out memory means for causing said rewriting means to rewrite in a selected one of said memory units, indicated by the drop-out information at the respective address to be storing video signals containing drop-out, the video signals being read-out of the memory unit then enabled for reading-out; and said drop-out memory means includes means operative upon the rewriting in said selected one of the memory units for erasing the drop-out information at the respective address of said drop-out memory means.
Claim 4
Dependent Claim
119 words
A time base corrector according to claim 2; further comprising velocity error memory means having a plurality of addresses respectively corresponding to said memory units for storing velocity error information in respect to velocity errors in the video signals as written in the respective memory units of said main memory means, and means responsive to said rewriting of video signals in a selected one of said memory units for substituting, at the respective address of said velocity error memory means, the velocity error information corresponding to the video signals being rewritten in said selected one of the memory units for the velocity error information corresponding to the video signals originally written in said selected one of the memory units.
Claim 5
Dependent Claim
85 words
A time base corrector according to claim 3; in which said velocity error memory means includes means responsive to said read addressing means of the system control means for selectively reading-out the velocity error information from the address thereof which corresponds to the one of said memory units then enabled for said reading-out of the video signals therefrom; and said read clock generating means includes means for modulating said read clock pulses with the velocity error information being read-out of said velocity error memory means.
Claim 6
Dependent Claim
142 words
A time base corrector according to claim 1; further comprising velocity error memory means having a plurality of addresses respectively corresponding to said memory units and including means responsive to said write addressing means of the system control means for selectively writing, at said addresses, velocity error information in respect to velocity errors occurring in the video signals as written in the respective memory units, and means responsive to said read addressing means of the system control means for selectively reading-out the velocity error information from the address of said velocity error memory means which corresponds to the one of said memory units then enabled for said reading-out of the video signals therefrom; and in which said read clock generating means includes means for modulating said read clock pulses with the velocity error information being read-out from said velocity error memory means.
Claim 7
Dependent Claim
195 words
A time base corrector according to claim 5; in which said write clock generating means includes a variable frequency oscillator having an output with a center frequency which is a multiple of a color subcarrier frequency of said video signals, phase-locked loop means receiving said oscillator output and horizontal sync signals separated from the video signals received by said input means for varying the frequency of said oscillator output in accordance with variations in the frequency of said separated horizontal sync signals, variable phase shifting means, means for applying said oscillator output to said variable phase shifting means so as to obtain said write clock pulses at the output of said variable phase shifting means, phase comparator means for comparing the phase of said output from the variable phase shifting means with the phase of burst signals at said subcarrier frequency separated from said video signals received by said input means and for providing a corresponding control signal to said variable phase shifting means; and further comprising means for applying said control signal from said phase comparator means to said velocity error memory means as said velocity error information to be written in the latter.
Claim 8
Dependent Claim
133 words
A time base corrector according to claim 1; in which said read addressing means includes read address generating means for providing main read addresses which are different from the write addresses simultaneously generated by said write addressing means, means for providing alternate read addresses which are one higher and one lower, respectively, than said main read addresses, means for selecting, as a spare read address, the one of said alternate read addresses which is also different from the write address then generated by said write addressing means, and means responsive to said drop-out information from said drop-out memory means for selecting, as a finally determined read address for said main memory control means, the one of said main and spare read addresses which identifies a memory unit storing video signals free of drop-out.
Claim 9
Dependent Claim
125 words
A time base corrector according to claim 7; in which said main memory control means includes rewriting means for selectively rewriting, in any one of said memory units, video signals being read-out of any other one of said memory units; said system control means further includes means for selecting the other of said main and spare read addresses as a possible rewrite address, and means responsive to the drop-out information in said drop-out memory means indicating storage in the memory unit identified by said possible rewrite address of video signals having drop-out for causing said rewriting means to rewrite, in said memory unit identified by said possible rewrite address, the video signals being read-out from the memory unit identified by said finally determined read address.
Claim 10
Dependent Claim
44 words
A time base corrector according to claim 8; in which said drop-out memory means includes means operative upon the rewriting in said memory unit identified by said possible rewrite address to erase the drop-out information at the respective address in said drop-out memory means.
Claim 11
Dependent Claim
122 words
A time base corrector according to claim 9; further comprising velocity error memory means having a plurality of addresses respectively corresponding to said memory units for storing velocity error information in respect to velocity errors in the video signals as written in the respective memory units of said main memory means, and means responsive to said rewriting of video signals in the one of said memory units identified by said possible rewrite address for substituting, at the respective address of said velocity error memory means, the velocity error information corresponding to the video signals being rewritten in said one of the memory units for the velocity error information corresponding to the video signals originally written in said one of the memory units.
Claim 12
Dependent Claim
91 words
A time base corrector according to claim 10; in which said velocity error memory means includes means responsive to said finally determined read address from the read addressing means of the system control means for selectively reading-out the velocity error information from the address thereof which corresponds to the one of said memory units then enabled for said reading-out of the video signals therefrom; and said read clock generating means includes means for modulating said read clock pulses with the velocity error information being read-out of said velocity error memory means.
Claim 13
Dependent Claim
141 words
A time base corrector according to claim 7; further comprising velocity error memory means having a plurality of addresses respectively corresponding to said memory units and including means responsive to said write addressing means of the system control means for selectively writing, at said addresses, velocity error information in respect to velocity errors occurring in the video signals as written in the respective memory units, and means responsive to said finally determined read address from the system control means for selectively reading-out the velocity error information from the address of said velocity error memory means which corresponds to the one of said memory units then identified by said finally determined read address; and in which said read clock generating means includes means for modulating said read clock pulses with the velocity error information being read-out from said velocity error memory means.
Claim 14
Dependent Claim
195 words
A time base corrector according to claim 12; in which said write clock generating means includes a variable frequency oscillator having an output with a center frequency which is a multiple of a color subcarrier frequency of said video signals; phase-locked loop means receiving said oscillator output and horizontal sync signals separated from the video signals received by said input means for varying the frequency of said oscillator output in accordance with variations in the frequency of said separated horizontal sync signals, variable phase shifting means, means for applying said oscillator output to said variable phase shifting means so as to obtain said write clock pulses at the output of said variable phase shifting means, phase comparator means for comparing the phase of said output from the variable phase shifting means with the phase of burst signals of said subcarrier frequency separated from said video signals received by said input means and for providing a corresponding control signal to said variable phase shifting means; and further comprising means for applying said control signal from said phase comparator means to said velocity error memory means as said velocity error information to be written in the latter.
References Cited (Backward Citations)
US3971063A
Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-17 | 1981-04-18 | 1981-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-17 | 1985-04-18 | 1985-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-17 | 1989-04-18 | 1989-10-18 | $7700.00 | Window Closed / Lapsed |