US4054842A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Channel gain imbalance compensation for FSK demodulator
Assignee: Boeing North American Inc
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Filing: 1977-01-19
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Granted: 1977-10-18
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Expires: 1997-01-19
Abstract
Abstract Channel gain imbalance in a FSK demodulator for receiving binary data is ameliorated by developing D. C. compensating signals indicative of the imbalance through the energy contained within a predetermined bandwidth of the demodulation channel pair output signals and arithmetically combining them with the channel output signals to counteract the imbalance bias contained therein.
Inventors
- 👤 William S. Elliott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:21
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/144; H04L27/148
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
115 words
In combination with an FSK demodulator having a pair of bandwidth limited channels formed with a pair of envelope detectors for providing D.C. output signals indicative of binary data and an arithmetic means for arithmetically combining the detector output signals to replicate the transmitted data bit stream, a gain imbalance compensating means, comprising: a pair of compensating circuits, each being connected to the output of a different one of the pair of detectors for providing a D.C. compensating signal proportional to the energy contained within a predetermined bandwidth of its associated detector output signal, and means for applying the compensating signals to the arithmetic means such that each counteracts its associated detector output applied thereto.
Claim 2
Dependent Claim
115 words
In combination with an FSK demodulator having a pair of bandwidth limited channels formed with a pair of envelope detectors for providing D.C. output signals indicative of binary data and an arithmetic means for arithmetically combining the detector output signals to replicate the transmitted data bit stream, a gain imbalance compensating means, comprising: a pair of compensating circuits, each being connected to the output of a different one of the pair of detectors for providing a D.C. compensating signal proportional to the energy contained within a predetermined bandwidth of its associated detector output signal, and means for applying the compensating signals to the arithmetic means such that each counteracts its associated detector output applied thereto.
Claim 3
Dependent Claim
20 words
The compensating means of claim 1 wherein the lower frequency of said predetermined bandwidth is greater than the data rate.
Claim 4
Dependent Claim
22 words
The compensating means of claim 2 wherein the upper frequency of said predetermined bandwidth is less than one-half of the channel bandwidth.
Claim 5
Dependent Claim
26 words
The compensating means of claim 3 wherein each of said compensating circuits includes a serially connected bandpass filter and envelope detector for affording the compensating signal.
Claim 6
Dependent Claim
42 words
The compensating means of claim 4 wherein each of said compensating circuits includes an amplifier for amplifying the compensating signal by an amount equal to the ratio of the bandwidth of its associated bandpass filter to the bandwidth of its associated channel.
Claim 7
Independent Claim
99 words
A method of providing gain imbalance compensation in an FSK demodulator having a pair of bandwidth limited channels formed with a pair of envelope detectors for providing D.C. output signals indicative of binary data and an arithmetic means for arithmetically combining the detector output signals to replicate the transmitted data bit stream, comprising: generating a pair of D.C. compensating signals, each being proportional to the energy contained within a predetermined bandwidth of a different one of the detector output signals, and applying said compensating signals to the arithmetic means such that each counteracts its associated detector output applied thereto.
Claim 8
Independent Claim
99 words
A method of providing gain imbalance compensation in an FSK demodulator having a pair of bandwidth limited channels formed with a pair of envelope detectors for providing D.C. output signals indicative of binary data and an arithmetic means for arithmetically combining the detector output signals to replicate the transmitted data bit stream, comprising: generating a pair of D.C. compensating signals, each being proportional to the energy contained within a predetermined bandwidth of a different one of the detector output signals, and applying said compensating signals to the arithmetic means such that each counteracts its associated detector output applied thereto.
Claim 9
Dependent Claim
19 words
The method of claim 6 wherein the lower frequency of said predetermined bandwith is greater than the data rate.
Claim 10
Dependent Claim
21 words
The method of claim 7 wherein the upper frequency of said predetermined bandwidth is less than one-half of the channel bandwidth.
Claim 11
Dependent Claim
151 words
A FSK demodulator for replicating a binary data bit stream from a FSK signal, comprising: a pair of mark and space channels, each having a serially connected bandpass filter and envelope detector for receiving the FSK signal and providing at the detector output a D.C. signal whenever a received bit conforms to its associated binary state; arithmetic means for arithmetically combining the outputs of said channel detectors to replicate the transmitted data bit stream; a pair of compensating circuits, each being connected to the output of a different one of said channel detectors and including a serially connected bandpass filter and envelope detector for providing at the output of said detector a D.C. compensating signal proportional to the energy contained within a predetermined bandwidth of its associated detector output signal, and means for applying the compensating signals to the arithmetic means such that each counteracts its associated detector output applied thereto.
Claim 12
Dependent Claim
151 words
A FSK demodulator for replicating a binary data bit stream from a FSK signal, comprising: a pair of mark and space channels, each having a serially connected bandpass filter and envelope detector for receiving the FSK signal and providing at the detector output a D.C. signal whenever a received bit conforms to its associated binary state; arithmetic means for arithmetically combining the outputs of said channel detectors to replicate the transmitted data bit stream; a pair of compensating circuits, each being connected to the output of a different one of said channel detectors and including a serially connected bandpass filter and envelope detector for providing at the output of said detector a D.C. compensating signal proportional to the energy contained within a predetermined bandwidth of its associated detector output signal, and means for applying the compensating signals to the arithmetic means such that each counteracts its associated detector output applied thereto.
Claim 13
Dependent Claim
19 words
The demodulator of claim 9 wherein the lower frequency of said predetermined bandwidth is greater than the data rate.
Claim 14
Dependent Claim
21 words
The demodulator of claim 10 wherein the upper frequency of said predetermined bandwidth is less than one-half of the channel bandwidth.
References Cited (Backward Citations)
US3341782A
Cited
US3248659A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-17 | 1981-04-18 | 1981-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-17 | 1985-04-18 | 1985-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-17 | 1989-04-18 | 1989-10-18 | $7700.00 | Window Closed / Lapsed |