Card-reader integrated circuit tester

Claim 2

Apparatus for checking one or more electrical parameters of a plurality of similar electronic circuit devices to be tested comprising: means for extracting from programming means information providing a plurality of differing tolerance comparison values for a parameter of such devices to be checked, said values represent differing classfication groups into which said plurality of similar electronic circuit devices are to be distributed; means for measuring the value of the parameter of one of said electronic circuit devices to be checked; means for comparing the measured value of the parameter with said plurality of differing tolerance comparison values to identify a classification group corresponding to said measured value; and means for displaying the results of said comparison.

Claim 3

The apparatus of claim 1 further including memory means for receiving information representatives of said plurality of differing comparison values for a parameter to be checked and storing the same for later recall when the parameter of interest is to be checked.

Claim 4

The apparatus of claim 2 wherein said memory means includes address locations for comparison values for differing parameters of an electronic circuit device to be tested.

Claim 5

The apparatus of claim 2 wherein said programming means is a plurality of programming cards, each having a first response area for indicia indicative of a comparison value for a parameter to be checked of an electronic circuit device and a second response area for indicia indicative of a selected classification group represented by said comparison value; and wherein said means for extracting said information from said programming means is a card reader which includes decoding means responsive to indicia in said response areas of said cards by entering information representative of the same into said memory means.

Claim 6

The apparatus of claim 4 wherein said first response area on said card includes applied thereto for each of a plurality of parameters of an electronic circuit device to be checked, a Hollerith code providing an array of potential comparison values in a decimal numercial system, and said decoding means includes a converter for converting a comparison value selected in decimal form from said Hollerith code to a binary digital code for entry into an address location therefor in said memory means.

Claim 7

The apparatus of claim 5 further including means for converting one of said measured value and said comparison value from said memory means to the same form as the other for said comparison.

Claim 8

The apparatus of claim 6 further including means responsive to a comparison by said comparison means indicating that the measured value of a parameter to be checked falls outside the tolerance limit against which it is checked by sequentially directing comparison of said measured value with the next succeeding tolerance comparison value for said measured value to identify a classification group into which the device having said measured parameter value is to be distributed.

Claim 9

Apparatus for checking the values of the input current flowing into the inverting and non-inverting input terminals of an operational amplifier to be tested comprising: a card reader for extracting from a programming card information providing comparison values for the input currents to be checked; means for measuring the values of said input currents of said operational amplifier to be checked including a pair of second operational amplifiers selected to have input currents at their respective inverting and non-inverting input terminals at least an order of magnitude less than the input currents expected of the operational amplifier to be tested, one of the inverting and non-inverting input terminals of both of said second operational amplifiers being connected to a reference voltage source and the other of said input terminals of each of said second operational amplifiers being connected respectively to an associated one of the inverting and non-inverting terminals of the operational amplifier to be tested; a feedback loop on each of said second operational amplifiers extending through a resistance between the output terminal thereof and the one of said inverting and non-inverting terminals thereof connected to said input terminal of said operational amplifier to be tested, whereby the voltage at the output terminal of each second operational amplifier is proportional to the input current to be measured thereby; means for comparing the voltage at the output terminal of each of said second operational amplifiers with the comparison values provided by said programming card; and means for displaying the results of said comparison.

Claim 10

Apparatus for checking the values of the input current flowing into the inverting and non-inverting input terminals of an operational amplifier to be tested comprising: a card reader for extracting from a programming card information providing comparison values for the input currents to be checked; means for measuring the values of said input currents of said operational amplifier to be checked including a pair of second operational amplifiers selected to have input currents at their respective inverting and non-inverting input terminals at least an order of magnitude less than the input currents expected of the operational amplifier to be tested, one of the inverting and non-inverting input terminals of both of said second operational amplifiers being connected to a reference voltage source and the other of said input terminals of each of said second operational amplifiers being connected respectively to an associated one of the inverting and non-inverting terminals of the operational amplifier to be tested; a feedback loop on each of said second operational amplifiers extending through a resistance between the output terminal thereof and the one of said inverting and non-inverting terminals thereof connected to said input terminal of said operational amplifier to be tested, whereby the voltage at the output terminal of each second operational amplifier is proportional to the input current to be measured thereby; means for comparing the voltage at the output terminal of each of said second operational amplifiers with the comparison values provided by said programming card; and means for displaying the results of said comparison.

Claim 11

A test circuit for measuring the input currents flowing into the inverting and non-inverting input terminals of an operational amplifier to be tested comprising: a pair of second operational amplifiers selected to have input currents at their respective inverting and non-inverting input terminals at least an order of magnitude less than the input currents expected of the operational amplifier to be tested, one of the inverting and non-inverting input terminals of both of said second operational amplifiers being connected to a reference voltage source and the other of said input terminals of each of said second operational amplifiers being connected respectively to an associated one of the inverting and non-inverting terminals of the operational amplifier to be tested; and a feedback loop on each of said second operational amplifiers extending through a resistance between the output terminal thereof and the one of said inverting and non-inverting input terminals thereof connected to said input terminal of said operational amplifier to be tested, whereby the voltage at the output terminal of each of said second operational amplifiers is proportional to the input current to be measured thereby.

Claim 12

A test circuit for measuring the input currents flowing into the inverting and non-inverting input terminals of an operational amplifier to be tested comprising: a pair of second operational amplifiers selected to have input currents at their respective inverting and non-inverting input terminals at least an order of magnitude less than the input currents expected of the operational amplifier to be tested, one of the inverting and non-inverting input terminals of both of said second operational amplifiers being connected to a reference voltage source and the other of said input terminals of each of said second operational amplifiers being connected respectively to an associated one of the inverting and non-inverting terminals of the operational amplifier to be tested; and a feedback loop on each of said second operational amplifiers extending through a resistance between the output terminal thereof and the one of said inverting and non-inverting input terminals thereof connected to said input terminal of said operational amplifier to be tested, whereby the voltage at the output terminal of each of said second operational amplifiers is proportional to the input current to be measured thereby.

Claim 13

The test circuit of claim 9 further including means connected to the output terminals of both of said second operational amplifiers for determining the average of the input currents flowing into the inverting and non-inverting input terminals of said operational amplifier to be tested.

Claim 14

The test circuit of claim 10 wherein said means for determining the average of said input currents flowing into said inverting and non-inverting input terminals includes a third operational amplifier having one of its inverting and non-inverting input terminals connected to a reference voltage source and the other one connected through a second resistance to the outputs of both of said second operational amplifiers; and a feedback loop on said third operational amplifier extending through a third resistance between the output terminal thereof and the one of said inverting and non-inverting input terminals connected to both of said output terminals of said second operational amplifiers, the ratio of said third resistance to said second resistance being selected to change by a predetermined proportionate amount the output voltage of said third operational amplifier relative to the combined output voltages of said second operational amplifiers connected to said one of said inverting and non-inverting terminals of said third operational amplifier.

Claim 15

The test circuit of claim 9 further including means connected to the output terminals of said second operational amplifiers for determining the difference between the input currents flowing into the inverting and non-inverting input terminals of said operational amplifier to be tested.

Claim 16

The test circuit of claim 12 wherein said means for determining the difference between the input currents flowing into said inverting and non-inverting input terminals of said operational amplifier to be tested includes a third operational amplifier having its inverting and non-inverting input terminals respectively connected to the output terminals of said second operational amplifiers; and a feedback loop extending through a resistance between the output terminal of said third operational amplifier and one of said inverting and non-inverting input terminals of said third operational amplifier whereby the voltage on said output terminal is indicative of the difference between the voltages applied by said second operational amplifiers to said input terminals of said third operational amplifier.

Claim 17

The operational amplifier of claim 12 further including means connected to the output terminals of both of said second operational amplifiers for determining the average of the input currents flowing into the inverting and non-inverting input terminals of said operational amplifier to be tested.

Claim 18

The operational amplifier of claim 14 wherein said means for determining the average of said input currents flowing into said inverting and non-inverting input terminals of said operational amplifier to be tested includes a third operational amplifier having one of its inverting and non-inverting input terminals connected to a reference voltage source and the other one of said input terminals connected through a second resistance to the outputs of both of said second operational amplifiers, and a feedback loop on said third operational amplifier extending through a third resistance between the output terminal thereof and the one of said inverting and non-inverting input terminals connected to both of said output terminals of said second operational amplifiers, the ratio of said third resistance to said second resistance being selected to change by a predetermined proportionate amount the output voltage of said third operational amplifier relative to the combined output voltages of said second operational amplifiers connected to said one of said inverting and non-inverting terminals of said third operational amplifier; and wherein said means for determining the difference between the input currents flowing into said inverting and non-inverting terminals includes an additional third operational amplifier having its inverting and non-inverting input terminals respectively connected to the output terminals of said second operational amplifiers, and a feedback loop extending through a resistance between the output terminal of said additional third operational amplifier and one of said inverting and non-inverting input terminals of said additional third operational amplifier whereby the voltage on said output terminal is indicative of the difference between the voltages applied by said second operational amplifiers to said input terminals of said additional third operational amplifier.

Claim 21

The method of claim 16 further including the step of storing the information extracted from said card providing said comparison value for later recall for said step of comparing the same with the measured value of said parameter of an electronic circuit device to be tested.

Claim 22

The method of claim 17 wherein said first response area is adapted to receive indicia indicative of pluralities of differing tolerance comparison values for a plurality of different parameters of an electronic circuit device to be tested, and said step of marking said first response area includes marking the same with indicia indicative of a selected comparison value for each of said plurality of parameters; said step of storing said information provided on said first response area for all of said parameters to be checked; said step of measuring the actual value of the parameter to be checked includes sequentially measuring the values of all of the parameters to be checked; and said step of comparing the measured value of the parameter with said comparison value includes sequentially recalling said tolerance comparison values from said memory for comparing each with the associated measured value of the parameter to be checked.

Claim 23

The method of claim 18 wherein said first response area on said programming card includes for each of said parameters a Hollerith code providing an array of potential comparison values in a decimal numerical system; and said step of extracting the information from said Hollerith code providing said comparison value on said first response area includes converting the information selected in decimal form from said Hollerith code to a binary digital code for said storing; and said step of sequentially comparing said comparison values for said parameters with said actual measured values, includes the step of converting said comparison values extracted from said memory to the same form as said measured values for said comparison.

Claim 24

The method of claim 19 wherein said steps of marking said card includes marking for each of said parameters a plurality of their respective cards on said first response areas with respective different tolerance comparison values representative of differing selected classification groups and marking the second response area on each of said cards to indicate the selected classification group represented by the indicia marked on said first response area; said step of feeding includes feeding said plurality of cards into said card reader for extraction therefrom of information providing said plurality of comparison values and said classification groups; and said step of comparing the measured values of said parameters with said comparison values includes the step of sequentially comparing each of said measured values with said plurality of differing tolerance comparison values to identify a classification group into which the device having said measured parameter value is to be distributed.