Circuit for electronic watches

Claim 2

An electronic timepiece having a digital display, an AM-PM indicator, an hour units counter, and means to enable selection by way of a control input between a 24 hour clock display mode and a 12 hour clock display mode, the improvement wherein said selection means comprises a first and a second flip-flop circuit, a decoder circuit coupled between outputs of said flip-flop circuits and a digital display and AM-PM indicator for driving said display and indicator, and logic means coupled with the counter and said flip-flop circuits and responsive to the control input for interconnecting said flip-flop circuits to form a counter for the tens of hours when said 24 hour clock display mode is selected, and for connecting said first flip-flop circuit to count the tens of hours and said second flip-flop circuit to control the AM-PM indicator when said 12 hour clock display mode is selected.

Claim 3

An electronic timepiece according to claim 1, wherein said logic means comprises: a first three-input AND gate, the inputs of which are connected in turn to said control input, to an output of said first flip-flop circuit and to a first output of said hour units counter, said first output of said counter delivering one pulse at a logic potential "1" each time when said hour units counter is at a logic state corresponding to the number "2"; a second three-input AND gate, the inputs of which are connected in turn through an inverter to said control input, to the output of said second flip-flop circuit and to a second output of said hour units counter, said second output of said counter delivering one pulse at a logic potential "1" each time when said hour units counter is at a logic state corresponding to the number "3"; a three-input NOR gate, the inputs of which are connected in turn to the output of said first flip-flop circuit, to the output of said second AND gate and to said control input; a two-input OR gate, the inputs of which are connected in turn to the output of said first AND gate and to the output of said NOR gate, the output of said OR gate being connected to the input of said second flip-flop circuit; and a two-input NOR gate, the inputs of which are connected in turn to the output of said AND gate and to a third output of said hour units counter, said third output of said counter delivering one pulse at a logic potential "1" each time when said hour units counter is at a logic state corresponding to the number "9", the output of said NOR gate being connected to the input of said first flop-flop circuit.

Claim 4

An electronic timepiece according to claim 2, wherein said decoder circuit comprises: a two-input AND gate, the imputs of which are connected in turn to the output of said second flip-flop circuit and through an inverter to the control input; and a two-input OR gate, the inputs of which are connected in turn to the output of said first flip-flop circuit and to the output of said two-input AND gate, the output of said two-input AND gate coupled to drive vertical segments and a lower left segment of a six-segment digital display for the tens of hours digit, the output of said decoder OR gate coupled to drive an upper right segment of said digital display, and the output of said first flip-flop circuit coupled to drive a lower right segment of said digital display.