Programmable microwave modulator

Claim 2

A programmable microwave modulator comprising: a. means for providing a radio frequency signal from a receiving antenna; b. programmable driver means for providing a linear analog signal that is predetermined both as to amplitude pattern and time period; c. attenuator means responsive to said linear analog signal for attenuating said radio frequency signal; and d. linearizing current driver means connected between said programmable driver means and said attenuator means for operating on said linear analog signal such that said radio frequency signal is attenuated by said attenuator means as a linear function of said linear analog signal.

Claim 3

The apparatus of claim 1 wherein said programmable driver means includes: a. a memory having a plurality of memory address locations for storing digital data; b. means for entering digital data into said memory, said digital data determining said amplitude pattern of said linear analog signal; c. means for sequentially addressing said memory and sequentially reading out the digital data stored in a predetermined number of memory address locations; d. means connected to said memory for converting the digital data read out of said memory to said linear analog signal.

Claim 4

The apparatus of claim 2 wherein said addressing and reading out means includes: a. a ripple counter generating a plurality of output signals inputing said memory, said plurality of ripple counter output signals defining the memory address location read out of said memory; b. means connected to said ripple counter for generating a series of timed clock pulses having a predetermined period, the period of said clock pulses determining the period of said linear analog signal, each said clock pulse advancing said ripple counter by one; c. means connected to said ripple counter for enabling and disabling said clock means from said ripple counter, thereby starting or stopping and resetting said ripple counter.

Claim 5

The apparatus of claim 3 wherein said enabling and disabling means includes: a. means for generating a start-reset pulse; b. means for generating a first stop pulse; c. a first monostable multivibrator having a first specific time constant associated therewith for generating a first logic one pulse and a first logic zero pulse simultaneously in response to said start-reset pulse; d. means connected to said plurality of ripple counter outputs for generating a second stop pulse when said predetermined number of memory address locations have been addressed and read out; e. a second monostable multivibrator having a second specific time constant associated therewith for generating a second logic zero pulse in response to said first and second stop pulses, said second time constant being larger than said first time constant; f. logic means connected to receive said first logic zero pulse, said first logic one pulse, and said second logic zero pulse for generating a continuous enable signal after receiving said first logic one pulse and said first logic zero pulse, for generating a continuous disable signal after receiving said second logic zero pulse, for generating a temporary disable signal after receiving said first logic one pulse and said first logic zero pulse for the second time without the intervening reception of said second logic zero pulse, said enable signal resetting said ripple counter and enabling said clock means, said disable signal resetting said ripple counter and disabling said clock means.

Claim 6

The apparatus of claim 4 wherein said logic means includes: a. a bistable multivibrator connected to receive said first and second logic zero pulses, said first and second logic zero pulses triggering said bistable into respective first and second stable conditions; b. gate means connected to said bistable multivibrator and connected to receive said first logic one pulse and said first logic zero pulse for generating said continuous enable signal when said bistable multivibrator is in said first stable condition, for generating said continuous disable signal when said bistable multivibrator is in said second stable condition, and for generating a temporary disable signal when said bistable multivibrator is in said first stable condition and said gate means receives said first logic one pulse and said first logic zero pulse.

Claim 7

The apparatus of claim 4 wherein said second stop pulse generating means includes a NAND gate having a plurality of inputs, one each connected to receive a respective output signal from said ripple counter.

Claim 8

The apparatus of claim 1 wherein said attenuator means includes a PIN attenuator.

Claim 9

The apparatus of claim 1 wherein said linearizing current driver means includes: a. means for generating the antilogarithm of said linear analog signal; and b. linear amplifying means for amplifying the antilogarithm of said linear analog signal, said antilogarithm of said linear analog signal inputing said attenuator means.

Claim 10

The apparatus of claim 8 wherein said antilogarithmic signal generating means includes a zener diode circuit.

Claim 11

A circuit for generating a linear analog signal having a predetermined amplitude pattern and period comprising: a. a memory having a plurality of memory address locations for storing digital data; b. means for entering digital data into said memory, said digital data determining said amplitude pattern of said linear analog signal; c. means for sequentially addressing said memory and sequentially reading out the digital data stored in a predetermined number of memory address locations; d. a ripple counter generating a plurality of output signals inputing said memory, said plurality of ripple counter output signals defining the memory address location read out of said memory; e. means connected to said ripple counter for generating a series of timed clock pulses having a predetermined period, the period of said clock pulses determining the period of said linear analog signal, each said clock pulse advancing said ripple counter by one; thereby sequentially addressing said memory and sequentially reading out the digital data stored in a predetermined number of memory address locations; f. means for generating a start-reset pulse; g. means for generating a first stop pulse; h. a first monostable multivibrator having a first specific time constant associated therewith for generating a first logic one pulse and a first logic zero pulse simultaneously in response to said start-reset pulse; i. means connected to said plurality of ripple counter outputs for generating a second stop pulse when said predetermined number of memory address locations have been addressed and read out; j. a second monostable multivibrator having a second specific time constant associated therewith for generating a second logic zero pulse in response to said first and second stop pulses, said second time constant being larger than said first time constant; k. logic means connected to receive said first logic zero pulse, said first logic one pulse, and said second logic zero pulse for generating a continuous enable signal after receiving said first logic one pulse and said first logic zero pulse, for generating a continuous disable signal after receiving said second logic zero pulse, for generating a temporary disable signal after receiving said first logic one pulse and said first logic zero pulse for the second time without the intervening reception of said second logic zero pulse, said enable signal resetting said ripple counter and enabling said clock means, said disable signal resetting said ripple counter and disabling said clock means; l. means connected to said memory for converting the digital data read out of said memory to said linear analog signal.

Claim 12

A circuit for generating a linear analog signal having a predetermined amplitude pattern and period comprising: a. a memory having a plurality of memory address locations for storing digital data; b. means for entering digital data into said memory, said digital data determining said amplitude pattern of said linear analog signal; c. means for sequentially addressing said memory and sequentially reading out the digital data stored in a predetermined number of memory address locations; d. a ripple counter generating a plurality of output signals inputing said memory, said plurality of ripple counter output signals defining the memory address location read out of said memory; e. means connected to said ripple counter for generating a series of timed clock pulses having a predetermined period, the period of said clock pulses determining the period of said linear analog signal, each said clock pulse advancing said ripple counter by one; thereby sequentially addressing said memory and sequentially reading out the digital data stored in a predetermined number of memory address locations; f. means for generating a start-reset pulse; g. means for generating a first stop pulse; h. a first monostable multivibrator having a first specific time constant associated therewith for generating a first logic one pulse and a first logic zero pulse simultaneously in response to said start-reset pulse; i. means connected to said plurality of ripple counter outputs for generating a second stop pulse when said predetermined number of memory address locations have been addressed and read out; j. a second monostable multivibrator having a second specific time constant associated therewith for generating a second logic zero pulse in response to said first and second stop pulses, said second time constant being larger than said first time constant; k. logic means connected to receive said first logic zero pulse, said first logic one pulse, and said second logic zero pulse for generating a continuous enable signal after receiving said first logic one pulse and said first logic zero pulse, for generating a continuous disable signal after receiving said second logic zero pulse, for generating a temporary disable signal after receiving said first logic one pulse and said first logic zero pulse for the second time without the intervening reception of said second logic zero pulse, said enable signal resetting said ripple counter and enabling said clock means, said disable signal resetting said ripple counter and disabling said clock means; l. means connected to said memory for converting the digital data read out of said memory to said linear analog signal.

Claim 13

The apparatus of claim 10 wherein said logic means includes: a. a bistable multivibrator connected to receive said first and second logic zero pulses, said first and second logic zero pulses triggering said bistable into respective first and second stable conditions; b. gate means connected to said bistable multivibrator and connected to receive said first logic one pulse and said first logic zero pulse for generating said continuous enable signal when said bistable multivibrator is in said first stable condition, for generating said continuous disable signal when said bistable multivibrator is in said second stable condition, and for generating a temporary disable signal when said bistable multivibrator is in said first stable condition and said gate means receives said first logic one pulse and said first logic zero pulse.

Claim 14

The apparatus of claim 10 wherein said second stop pulse generating means includes a NAND gate having a plurality of inputs, one each connected to receive a respective output signal from said ripple counter.