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US4048578A Expired / Lapsed US ⏱️ 0.0 years remaining

R.f. amplifier circuit

Assignee: Hitachi Ltd
•
Filing: 1976-10-27
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Granted: 1977-09-13
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Expires: 1996-10-27
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Abstract

Abstract An R.F. amplifier circuit having a high selectivity with a simple and inexpensive construction is provided. An R.F. choke coil acting as a bias supplying element is connected to a collector of an amplifying transistor to supply it with an optimum biasing current for a high electric field strength. A first capacitor is connected in parallel, at a high frequency, with the R.F. choke coil, which is connected to an LC tuning circuit through a second capacitor. A resonance frequency of the R.F. choke coil and the first capacitor is chosen to be sufficiently lower than that of the LC tuning circuit to maintain a single tuned circuit while at the same time an output impedance of the amplifying transistor is stepped up by the first and second capacitors to insure a high quality factor.

Inventors

  • 👤 Hiroshi Kimura

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 18:43
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/191

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 93 words
An R.F. amplifier circuit having an LC parallel tuning circuit at an output thereof comprising; an R.F. choke coil connected between an output electrode of an amplifying transistor and a power supply and having a sufficiently low D.C. resistance, a first capacitor connected between said output electrode and a ground across said amplifying transistor, and a second capacitor connected between said output electrode and said LC parallel tuning circuit, a resonance frequency of said first capacitor and said coil being selected to be sufficiently lower than a resonance frequency of said tuning circuit.
Claim 2
Dependent Claim 93 words
An R.F. amplifier circuit having an LC parallel tuning circuit at an output thereof comprising; an R.F. choke coil connected between an output electrode of an amplifying transistor and a power supply and having a sufficiently low D.C. resistance, a first capacitor connected between said output electrode and a ground across said amplifying transistor, and a second capacitor connected between said output electrode and said LC parallel tuning circuit, a resonance frequency of said first capacitor and said coil being selected to be sufficiently lower than a resonance frequency of said tuning circuit.
Claim 3
Dependent Claim 110 words
An R.F. amplifier circuit comprising; an R.F. amplifying transistor for amplifying an R.F. input signal applied to a base thereof, a driving power supply for said transistor, an R.F. choke coil connected between a collector of said transistor and said power supply for supplying a collector bias current therethrough to said transistor, a first capacitor connected between the collector and an emitter of said transistor, a parallel resonance circuit including parallel connected inductor and capacitor, at least one of inductance and capacitance thereof being variable, and means including a second capacitor for connecting said parallel resonance circuit across the collector and the emitter of said transistor through said second capacitor.
Claim 4
Dependent Claim 110 words
An R.F. amplifier circuit comprising; an R.F. amplifying transistor for amplifying an R.F. input signal applied to a base thereof, a driving power supply for said transistor, an R.F. choke coil connected between a collector of said transistor and said power supply for supplying a collector bias current therethrough to said transistor, a first capacitor connected between the collector and an emitter of said transistor, a parallel resonance circuit including parallel connected inductor and capacitor, at least one of inductance and capacitance thereof being variable, and means including a second capacitor for connecting said parallel resonance circuit across the collector and the emitter of said transistor through said second capacitor.

References Cited (Backward Citations)

US1956121A Cited
US2542087A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-09-12 1981-03-14 1981-09-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-09-12 1985-03-14 1985-09-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-09-12 1989-03-14 1989-09-13 $7700.00 Window Closed / Lapsed

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