Resistor-controlled circuit for improving bandwidth of current gain cells

Claim 1

A gain-cell circuit with transistors each having a base, a collector and an emitter for providing increased signal bandwidth by utilizing the capacitance inherent in the transistors to achieve pole-zero cancellation, the circuit comprising: a first matchhed differential pair of common emitter transistors for producing a first pair of intermediate signals at its collectors and forming a dominant pole in response to a bias current applied to its emitters and differential input signal currents applied to its bases; a second matched pair of common-base transistors, the emitters of which are coupled to the bases of the transistors of the first matched pair and coupled to receive the differential input signal currents for producing a second pair of intermediate signals at its collectors, the collectors of said second matched pair of transistors being cross-coupled to the collectors of the first matched pair of transistors for producing differential output signal currents by combining selected ones of the first pair of intermediate signals with selected ones of the second pair of intermediate signals; and a matched pair of resistor means each coupled to the base of one of said second matched pair of common base transistors and coupled to a common reference voltage source for causing the second matched pair of transistors to form a zero substantially cancelling the dominant pole formed by the first matched pair of transistors.