US4048574A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and a device for eliminating the residual error voltage of an amplifier
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1976-06-25
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Granted: 1977-09-13
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Expires: 1996-06-25
Abstract
Abstract The connections between the two inputs of an amplifier and the two outputs of a signal source as well as between the outputs of the amplifier and the inputs of a downstream output element into which the amplifier delivers a signal are inverted periodically and simultaneously and integration is carried out between the outputs of the amplifier and the inputs of the output element. In addition, the inputs of the amplifier are short-circuited periodically, the frequencies of inversion and of short-circuiting being multiples of each other.
Inventors
- 👤 Daniel Barbier
- 👤 Jean-Michel Ittel
- 👤 Robert Poujois
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:00
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; H03F3/45928; H03F3/45968; H03F3/38; H03F2200/00; H03F2200/81
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
86 words
A method of elimination of the residual error voltage of an amplifier having two inputs supplied from a signal source and two outputs, said amplifier being intended to deliver a signal into an output element downstream of said amplifier, wherein the connections between the inputs of said amplifier are periodically inverted with said source and the outputs of said amplifier are inverted with said output element and wherein an integration is carried out between the outputs of said amplifier and the inputs of the output element.
Claim 2
Independent Claim
86 words
A method of elimination of the residual error voltage of an amplifier having two inputs supplied from a signal source and two outputs, said amplifier being intended to deliver a signal into an output element downstream of said amplifier, wherein the connections between the inputs of said amplifier are periodically inverted with said source and the outputs of said amplifier are inverted with said output element and wherein an integration is carried out between the outputs of said amplifier and the inputs of the output element.
Claim 3
Dependent Claim
32 words
A method according to claim 1, wherein said method further consists in periodically short-circuiting the inputs of said amplifier, the frequencies of the inversion and short-circuiting operations being multiples of each other.
Claim 4
Independent Claim
118 words
A method of elimination of the residual error voltage of an amplifier having two inputs supplied from a signal source and two outputs provided with a storage element, said amplifier being intended to deliveer a signal into a downstream output element of said amplifier, wherein said method consists in periodically and simultaneously inverting the connections between the inputs of said amplifier with said source and in inverting the outputs of said amplifier with said output element, wherein the inputs of said amplifier are short-circuited periodically, the frequencies of the inversion and short-circuiting operations being multiples of each other and wherein an integration is carried out between the outputs of said amplifier and the inputs of the output element.
Claim 5
Independent Claim
118 words
A method of elimination of the residual error voltage of an amplifier having two inputs supplied from a signal source and two outputs provided with a storage element, said amplifier being intended to deliveer a signal into a downstream output element of said amplifier, wherein said method consists in periodically and simultaneously inverting the connections between the inputs of said amplifier with said source and in inverting the outputs of said amplifier with said output element, wherein the inputs of said amplifier are short-circuited periodically, the frequencies of the inversion and short-circuiting operations being multiples of each other and wherein an integration is carried out between the outputs of said amplifier and the inputs of the output element.
Claim 6
Dependent Claim
161 words
A method according to claim 3, wherein the inversion operation is carried out in a number of steps: initially the two input terminals A and B of the amplifier are connected respectively to the two output terminals C and D of the source and similarly the two outputs A' and B' of the amplifier are connected respectively to the inputs C' and D' of the element located downstream of said amplifier, whereupon the connections between the terminals A, B, C, D, A', B', C', D' are disconnected, the inputs of said amplifier are then short-circuited and after disconnecting the input short-circuit of the amplifier, the terminals of said amplifier and of the downstream element are connected by reversing them with respect to the preceding arrangement or by connecting A and D and B and C and similarly A' and D', B' and C', whereupon the operations of inversion and short-circuiting are repeated in the same order after a predetermined time interval.
Claim 7
Dependent Claim
40 words
A method according to claim 3, wherein the operation of inversion of the connections at the input and at the output of the amplifier is carried out during a time interval in which the inputs of said amplifier are short-circuited.
Claim 8
Dependent Claim
97 words
An amplifying device, wherein said device comprises: at least one amplifier having two inputs A and B and two outputs A' and B', said amplifier being provided with a storage element, means for inverting the connections of the inputs A and B of said amplifier with the outputs C and D of a signal source and for simultaneously inverting the connections of the outputs A' and B' of said amplifier with the inputs C' and D' of the downstream element of said amplifier, means for short-circuiting the inputs of said amplifier during a predetermined period of time.
Claim 9
Dependent Claim
97 words
An amplifying device, wherein said device comprises: at least one amplifier having two inputs A and B and two outputs A' and B', said amplifier being provided with a storage element, means for inverting the connections of the inputs A and B of said amplifier with the outputs C and D of a signal source and for simultaneously inverting the connections of the outputs A' and B' of said amplifier with the inputs C' and D' of the downstream element of said amplifier, means for short-circuiting the inputs of said amplifier during a predetermined period of time.
Claim 10
Dependent Claim
15 words
A device according to claim 6, wherein said storage element comprises at least one capacitor.
Claim 11
Dependent Claim
60 words
An amplifying device according to claim 6, wherein said devce comprises N amplifiers, each output of an amplifier being connected to the input of a following downstream amplifier by means of a capacitor, means for short-circuiting the input of each amplifier and means for inverting in synchronism the inputs of the first amplifier and the outputs of the last amplifier.
Claim 12
Dependent Claim
42 words
A device according to claim 6, wherein said device comprises means for inverting the connections of the inputs and of the outputs of the amplifier or amplifiers during the time interval in which the inputs of the amplifier or amplifiers are short-circuited.
Claim 13
Dependent Claim
34 words
A device according to claim 6, wherein said device comprises means for inverting the input connections of said amplifier or of said amplifiers when the input or inputs of said amplifiers are not short-circuited.
Claim 14
Dependent Claim
86 words
A device according to claim 6, wherein said device comprises field-effect transistors inserted in series in the inputs and outputs of said amplifiers, said transistors being capable of establishing on the one hand the connection of the amplifier or amplifiers to the signal source and to the downstream elements and on the other hand of short-circuiting the input of each amplifier, said transistors being driven by biasing signals applied to the transistor gates and a clock being intended to deliver the recurrent signals to said gates.
References Cited (Backward Citations)
US3737793A
Cited
US3988689A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-12 | 1981-03-14 | 1981-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-12 | 1985-03-14 | 1985-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-12 | 1989-03-14 | 1989-09-13 | $7700.00 | Window Closed / Lapsed |