US4044272A
Expired / Lapsed
US
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Fail-safe electronic time delay circuit
Assignee: Hitachi Rail STS USA Inc
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Filing: 1976-08-12
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Granted: 1977-08-23
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Expires: 1996-08-12
Abstract
Abstract This disclosure relates to a fail-safe time delay circuit for providing a definite time interval. The time delay circuit includes a resistance-capacitance charging network which is connected to a source of a d.c. supply source by a switching device. The potential charge developed on the capacitor powers an inverter to produce a.c. signals having a given frequency. The a.c. signal is fed to a multi-stage tuned amplifier having a resonant circuit tuned to the given frequency. The amplified a.c. signals are applied to a voltage doubling network which normally energizes a load and which maintains the load energized for no longer than the definite time interval after the opening of the switching device.
Inventors
- 👤 John O. G. Darrow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:54
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/28
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
99 words
A fail-safe time delay circuit comprising, a. a source of d.c. voltage, b. a resistance-capacitance network coupled to said d.c. voltage source for charging said capacitance to said d.c. voltage, c. an inverter coupled to said resistance-capacitance network for converting said d.c. voltage charge to a.c. signals, d. a tuned amplifier coupled to said inverter for amplifying said a.c. signals, e. a rectifier coupled to said tuned amplifier, and f. a load coupled to said rectifier for normally being energized and for being deenergized a definite time interval after the source of d.c. voltage is disconnected from the circuit.
Claim 2
Dependent Claim
99 words
A fail-safe time delay circuit comprising, a. a source of d.c. voltage, b. a resistance-capacitance network coupled to said d.c. voltage source for charging said capacitance to said d.c. voltage, c. an inverter coupled to said resistance-capacitance network for converting said d.c. voltage charge to a.c. signals, d. a tuned amplifier coupled to said inverter for amplifying said a.c. signals, e. a rectifier coupled to said tuned amplifier, and f. a load coupled to said rectifier for normally being energized and for being deenergized a definite time interval after the source of d.c. voltage is disconnected from the circuit.
Claim 3
Dependent Claim
17 words
A fail-safe time circuit, as defined in claim 1, wherein said inverter is a free-running solid-state multivibrator.
Claim 4
Dependent Claim
17 words
A fail-safe time delay circuit, as defined in claim 1, wherein said inverter is an oscillating circuit.
Claim 5
Dependent Claim
29 words
A fail-safe time delay circuit, as defined in claim 1, wherein said tuned amplifier includes a parallel tank circuit connected to the output circuit of a common emitter stage.
Claim 6
Dependent Claim
20 words
A fail-safe time delay circuit, as defined in claim 1, wherein said tuned amplifier includes a plurality of transistor stages.
Claim 7
Dependent Claim
27 words
A fail-safe time delay circuit, as defined in claim 1, wherein said rectifier includes a voltage doubling network is coupled to the output of said tuned amplifier.
Claim 8
Dependent Claim
29 words
A fail-safe time delay circuit, as defined in claim 1, wherein said voltage doubling network is coupled to a pair of complementary transistors connected in an emitter follower configuration.
Claim 9
Dependent Claim
23 words
A fail-safe time delay circuit, as defined in claim 1, wherein said inverter includes a pair of transistors coupled as a bistable multivibrator.
Claim 10
Dependent Claim
28 words
A fail-safe time delay circuit, as defined in claim 1, wherein a switch contact is coupled to said source of d.c. voltage for disconnecting said d.c. voltage source.
Claim 11
Dependent Claim
25 words
A fail-safe time delay circuit, as defined in claim 6, wherein said voltage doubling network includes a pair of diodes and a pair of capacitors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-22 | 1981-02-21 | 1981-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-22 | 1985-02-21 | 1985-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-22 | 1989-02-21 | 1989-08-23 | $7700.00 | Window Closed / Lapsed |