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US4042854A Expired / Lapsed US ⏱️ 0.0 years remaining

Flat panel display device with integral thin film transistor control system

Assignee: Townsend and Townsend Khourie and Crew
•
Filing: 1975-11-21
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Granted: 1977-08-16
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Expires: 1995-11-21
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Abstract

Abstract A large area integrated solid-state flat panel display is detailed in which thin film transistor addressing and drive circuitry is provided at each individual picture point with a display medium. The preferred display medium is an electroluminescent phosphor layer. An insulating layer of laminated photoresist is disposed over all electrical circuit elements except the electroluminescent drive electrodes.

Inventors

  • 👤 Fang-Chen Luo
  • 👤 Thomas P. Brody

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 09:42
CPC Classifications
H; H04; H04N; H04N3/00; H04N3/10; H04N3/14; G; G09; G09G; G09G3/00; G09G3/20; G09G3/22; G09G3/30; G09G3/32; G09G2300/00; G09G2300/08; G09G2300/0809; G09G2300/0842

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 174 words
An electroluminescent display panel comprising; a. a planar substrate; b. an array of spaced apart thin film transistor control circuitry disposed on the substrate; c. an orthogonal matrix of rows and columns of switching signal, information signal, and power bus bars disposed on the substrate interconnecting and defining an array of unit display cells, each unit display cell including an individual thin film transistor control circuit; d. a first electroluminescent electrode disposed on the substrate as part of each unit display cell and interconnected with the transistor control circuit; e. a relatively thick laminated polymerized in place photoresist insulator layer disposed over the thin film transistor control circuitry and over interconnecting bus bars but not over the first electroluminescent electrodes; f. a layer of electroluminescent material disposed over the entire area of the display panel over the insulator layer and in intimate contact with the individual first electroluminescent electrodes, which electroluminescent layer has a planar, smooth top surface; g. a light transmissive common electrode deposited atop the electroluminescent layer and in intimate contact therewith.
Claim 2
Dependent Claim 174 words
An electroluminescent display panel comprising; a. a planar substrate; b. an array of spaced apart thin film transistor control circuitry disposed on the substrate; c. an orthogonal matrix of rows and columns of switching signal, information signal, and power bus bars disposed on the substrate interconnecting and defining an array of unit display cells, each unit display cell including an individual thin film transistor control circuit; d. a first electroluminescent electrode disposed on the substrate as part of each unit display cell and interconnected with the transistor control circuit; e. a relatively thick laminated polymerized in place photoresist insulator layer disposed over the thin film transistor control circuitry and over interconnecting bus bars but not over the first electroluminescent electrodes; f. a layer of electroluminescent material disposed over the entire area of the display panel over the insulator layer and in intimate contact with the individual first electroluminescent electrodes, which electroluminescent layer has a planar, smooth top surface; g. a light transmissive common electrode deposited atop the electroluminescent layer and in intimate contact therewith.
Claim 3
Dependent Claim 21 words
The electroluminescent display panel as specified in claim 1, wherein a light transmissive faceplate is provided over the light transmissive electrode.
Claim 4
Dependent Claim 20 words
The electroluminescent display panel as specified in claim 2, wherein the faceplate is peripherally hermetically sealed to the planar substrate.
Claim 5
Dependent Claim 29 words
The electroluminescent display panel as specified in claim 1, wherein the laminated photoresist insulator is substantially photopolymerized acrylate in a thickness of from about 0.5 mil to 5 mils.

References Cited (Backward Citations)

US3330982A Cited
US3379931A Cited
US3512041A Cited
US3786307A Cited
US3885196A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-08-15 1981-02-14 1981-08-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-08-15 1985-02-14 1985-08-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-08-15 1989-02-14 1989-08-16 $7700.00 Window Closed / Lapsed

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