US4042787A
Expired / Lapsed
US
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Output processing and output coupling circuit for a digital tone receiver
Assignee: Telex Computer Products Inc
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Filing: 1976-05-17
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Granted: 1977-08-16
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Expires: 1996-05-17
Abstract
Abstract A circuit is provided to convert a set of mutually exclusive digital signals representing presence or absence of individual tones of a Dual Tone Multiple Frequency (DTMF), or 2-of-8 signal, system into a four digit binary code word. Each different four bit word combination represents a different valid tone combination of the DTMF signal system. The four bit binary code word is represented by digits stored in an output register which serves as an output buffer. The loading of the output register is controlled by a single, multiple function signal which: (i) incorporates a coincidence timing function, (ii) provides a validity check which is also an integral part of the logical operation of the conversion, and (iii) causes the output signal to be interrupted upon a shift in input tones even though the shift in input tones may occur without interruption. The validity check which is also an integral part of the logical conversion further enables a construction which is readily modifiable after manufacture to accommodate different modes of use of a 2-of-8 signal system. The single, multiple function signal is further useful as an auxiliary output signal to aid in the processing of the four digit binary code word output signal, which takes place in the utilization circuit.
Inventors
- 👤 Glenn L. Richards
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 06:29
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/457
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
391 words
For use in a tone signal system of a type in which a valid signal is characterized by the concurrent presence in first and second frequency channels of a selectively signalled first tone and a selectively signalled second tone, respectively, said first and second selectively signalled tones being one of a first tone set which may be present in said first channel and one of a second tone set which may be present in said second channel, respectively, the combination including: a. first and second channel tone detectors operative to detect said first and second selectively signalled tones, respectively, said detectors each having a set of outputs corresponding to the tone set which may be present in the respective channel, each output of each set having two output states comprising an output state indicating presence of the corresponding tone and an output indicating absence of the corresponding tone, b. a set of tone combination detector gates, said set of detector gates corresponding in number and individual associations to a predetermined set of combinations of one individual tone of the first tone set and of another individual tone of the second tone set, each detector gate of said set having first and second gate inputs connected to a distinct output of the first channel tone detector and to a distinct output of the second channel tone detector, respectively, each detector gate of said set being operative to propogate an ASSERTION state to its output when an ASSERTION state is simultaneously received at both of its gate inputs, c. output buffer means for providing an output signal representing a detected tone combination of one individual tone of said first tone set and another individual tone of said second tone set, d. means operatively connecting the outputs of the detector gates and the output buffer means, and e. means for enabling said output signal of said output buffer means in response to presence of an ASSERTION state among the outputs of said set of detector gates and for interrupting an enablement of said output signal of said output buffer means in response to each new appearance at the output of any detector gate of an ASSERTION state, the operation to enable said output signal of said output buffer means being subordinate to the operation to interrupt said output signal of said output buffer means.
Claim 2
Dependent Claim
391 words
For use in a tone signal system of a type in which a valid signal is characterized by the concurrent presence in first and second frequency channels of a selectively signalled first tone and a selectively signalled second tone, respectively, said first and second selectively signalled tones being one of a first tone set which may be present in said first channel and one of a second tone set which may be present in said second channel, respectively, the combination including: a. first and second channel tone detectors operative to detect said first and second selectively signalled tones, respectively, said detectors each having a set of outputs corresponding to the tone set which may be present in the respective channel, each output of each set having two output states comprising an output state indicating presence of the corresponding tone and an output indicating absence of the corresponding tone, b. a set of tone combination detector gates, said set of detector gates corresponding in number and individual associations to a predetermined set of combinations of one individual tone of the first tone set and of another individual tone of the second tone set, each detector gate of said set having first and second gate inputs connected to a distinct output of the first channel tone detector and to a distinct output of the second channel tone detector, respectively, each detector gate of said set being operative to propogate an ASSERTION state to its output when an ASSERTION state is simultaneously received at both of its gate inputs, c. output buffer means for providing an output signal representing a detected tone combination of one individual tone of said first tone set and another individual tone of said second tone set, d. means operatively connecting the outputs of the detector gates and the output buffer means, and e. means for enabling said output signal of said output buffer means in response to presence of an ASSERTION state among the outputs of said set of detector gates and for interrupting an enablement of said output signal of said output buffer means in response to each new appearance at the output of any detector gate of an ASSERTION state, the operation to enable said output signal of said output buffer means being subordinate to the operation to interrupt said output signal of said output buffer means.
Claim 3
Dependent Claim
46 words
A circuit as defined in claim 1, wherein; a. said means for enabling said output signal of said output buffer means and for interrupting an enablement of said output signal of said output buffer means does same by enabling and inhibiting, respectively, the output buffer means.
Claim 4
Dependent Claim
382 words
A digital tone receiver circuit for receiving a set of digital signals which when respectively in their ASSERTION state represent the detection of a respective tone of a corresponding predetermined set of tones, and for converting said digital signals into a tone receiver output signal representing a detected tone combination, said circuit comprising: a. a set of input terminals for receiving the set of digital signals, said set of input terminals corresponding in number and individual associations to said set of digital signals, b. a set of tone combination detector gates, said set of detector gates corresponding in number and individual associations to a predetermined set of tone combinations, each detector gate of said set having a plurality of gate inputs connected to different input terminals, each detector gate of said set being operative to propogate an ASSERTION state to its output when an ASSERTION state is received at all of its gate inputs, c. output buffer means for providing a tone receiver output signal representing a detected tone combination of said predetermined set of combinations, d. means operatively connecting the outputs of the detector gates and the output buffer means, e. means for enabling said tone receiver output signal in response to presence of an ASSERTION state among the outputs of said set of detector gates and for interrupting an enablement of said tone receiver output signal in response to each new appearance at the output of any detector gate of an ASSERTION state, the operation to enable said tone receiver output signal being subordinate to the operation to interrupt said tone receiver output signal, f. tone detector means of a type which provides a tone combination change pulse in response to each detection of a new tone combination of said predetermined set of tone combinations, and g. said means for enabling said tone receiver output signal including logic means operative to provide an ASSERTION state at its output only in response to presence of an ASSERTION state among the outputs of said detector gates and in absence of a tone combination change pulse, h. the signal at the output of said logic means being operative to enable said tone receiver output signal when in its ASSERTION state and to interrupt said tone receiver output signal when in its NEGATION state.
Claim 5
Dependent Claim
382 words
A digital tone receiver circuit for receiving a set of digital signals which when respectively in their ASSERTION state represent the detection of a respective tone of a corresponding predetermined set of tones, and for converting said digital signals into a tone receiver output signal representing a detected tone combination, said circuit comprising: a. a set of input terminals for receiving the set of digital signals, said set of input terminals corresponding in number and individual associations to said set of digital signals, b. a set of tone combination detector gates, said set of detector gates corresponding in number and individual associations to a predetermined set of tone combinations, each detector gate of said set having a plurality of gate inputs connected to different input terminals, each detector gate of said set being operative to propogate an ASSERTION state to its output when an ASSERTION state is received at all of its gate inputs, c. output buffer means for providing a tone receiver output signal representing a detected tone combination of said predetermined set of combinations, d. means operatively connecting the outputs of the detector gates and the output buffer means, e. means for enabling said tone receiver output signal in response to presence of an ASSERTION state among the outputs of said set of detector gates and for interrupting an enablement of said tone receiver output signal in response to each new appearance at the output of any detector gate of an ASSERTION state, the operation to enable said tone receiver output signal being subordinate to the operation to interrupt said tone receiver output signal, f. tone detector means of a type which provides a tone combination change pulse in response to each detection of a new tone combination of said predetermined set of tone combinations, and g. said means for enabling said tone receiver output signal including logic means operative to provide an ASSERTION state at its output only in response to presence of an ASSERTION state among the outputs of said detector gates and in absence of a tone combination change pulse, h. the signal at the output of said logic means being operative to enable said tone receiver output signal when in its ASSERTION state and to interrupt said tone receiver output signal when in its NEGATION state.
Claim 6
Dependent Claim
78 words
A circuit as defined in claim 3, wherein; a. said means for enabling the tone receiver output signal and for interrupting an enablement of said tone receiver output signal includes timer means operatively responsive to the signal at the output of said logic means, said timer means being operative to interrupt an enablement of the tone receiver output signal until an ASSERTION state is present at the output of said logic means for a predetermined duration of time.
Claim 7
Dependent Claim
62 words
A circuit in accordance with claim 4, wherein; a. said timer means is a counter having a reset input to which is connected the output of said logic means and having a count stepping input to which is drivingly connected a clock pulse signal, the construction and arrangement being such that a NEGATION state applied to said reset input resets the counter.
Claim 8
Dependent Claim
83 words
A circuit as defined in claim 4, wherein; a. said output buffer means comprises a set of digit store devices which when loaded with digits compositely represent the detected tone combination, b. said timer means having an output and being operative to provide an ASSERTION state at said output after said predetermined duration of time, c. the loading of the digital store devices with digits being actuated by the leading edge of an ASSERTION state pulse at the output of said timer means.
Claim 9
Dependent Claim
63 words
A circuit as defined in claim 6, wherein; a. the trailing edge of an ASSERTION state pulse at the output of said timer means is coupled to a utilization circuit means as an auxiliary indication that the set of digit store devices are loaded with digits and therefore the tone receiver output signal is ready to be utilized by the utilization circuit means.
Claim 10
Dependent Claim
357 words
A digital tone receiver circuit for receiving a set of digital signals which when respectively in their ASSERTION state represent the detection of a respective tone of a corresponding predetermined set of tones, and for converting said digital signals into a tone receiver output signal representing a detected tone combination, said circuit comprising: a. a set of input terminals for receiving the set of digital signals, said set of input terminals corresponding in number and individual associations to said set of digital signals, b. a set of N tone combination detector gates, said set of detector gates corresponding in number and individual associations to a predetermined set of tone combinations, each detector gate of the set having a plurality of gate inputs connected to different input terminals of said set of input terminals, each detector gate of said set being operative to propogate an ASSERTION state to its output when an ASSERTION state is received at all of its gate inputs, c. output buffer means for providing a tone receiver output signal representing a detected tone combination of said predetermined set of combinations, d. means operatively connecting the outputs of the detector gates and the output buffer means, e. means for enabling the tone receiver output signal, said means for enabling the tone receiver output signal being operative to enable the same in response to presence of an ASSERTION state among the outputs of said set of detector gates, f. the representation of the detected tone combination provided by the output buffer means is in a predetermined digital format different from that at the outputs of said set of N detector gates, g. said means operatively connecting the outputs of the detector gates and the output buffer means including encoder means for encoding the outputs of the set of N detector gates into said predetermined digital format, said encoder means being of a type which performs such encoding in accordance with the outputs of only N-1 detector gates, and h. said means for enabling said tone receiver output signal being responsive to both the output of said encoder means and the output of the Nth decoder gate.
Claim 11
Dependent Claim
357 words
A digital tone receiver circuit for receiving a set of digital signals which when respectively in their ASSERTION state represent the detection of a respective tone of a corresponding predetermined set of tones, and for converting said digital signals into a tone receiver output signal representing a detected tone combination, said circuit comprising: a. a set of input terminals for receiving the set of digital signals, said set of input terminals corresponding in number and individual associations to said set of digital signals, b. a set of N tone combination detector gates, said set of detector gates corresponding in number and individual associations to a predetermined set of tone combinations, each detector gate of the set having a plurality of gate inputs connected to different input terminals of said set of input terminals, each detector gate of said set being operative to propogate an ASSERTION state to its output when an ASSERTION state is received at all of its gate inputs, c. output buffer means for providing a tone receiver output signal representing a detected tone combination of said predetermined set of combinations, d. means operatively connecting the outputs of the detector gates and the output buffer means, e. means for enabling the tone receiver output signal, said means for enabling the tone receiver output signal being operative to enable the same in response to presence of an ASSERTION state among the outputs of said set of detector gates, f. the representation of the detected tone combination provided by the output buffer means is in a predetermined digital format different from that at the outputs of said set of N detector gates, g. said means operatively connecting the outputs of the detector gates and the output buffer means including encoder means for encoding the outputs of the set of N detector gates into said predetermined digital format, said encoder means being of a type which performs such encoding in accordance with the outputs of only N-1 detector gates, and h. said means for enabling said tone receiver output signal being responsive to both the output of said encoder means and the output of the Nth decoder gate.
Claim 12
Dependent Claim
55 words
A circuit as defined in claim 8, wherein; a. said encoder means comprises a set of OR-TYPE gates, and b. said means for enabling the tone receiver output signal including another OR-TYPE gate having as individual inputs thereto the respective outputs of said set of OR-TYPE gates and the output of said Nth detector gate.
Claim 13
Dependent Claim
108 words
A circuit as defined in claim 8, wherein; a. said set of N detector gates includes a predetermined subset of detector gates each of which has another gate input which is in addition to its plurality of gate inputs connected to the input terminals, b. the another gate input of each detector gate of the subset being commonly connected to an adjustable logic signal means, said adjustable logic signal means being of a type which may be adjusted from one condition in which it applies an ASSERTION state to the another gate inputs to another condition in which it applies a NEGATION state to the another gate inputs.
Claim 14
Dependent Claim
339 words
A digital tone receiver circuit for receiving a set of digital signals which when respectively in their ASSERTION state represent the detection of a respective tone of a corresponding predetermined set of tones, and for converting said digital signals into a tone receiver output signal representing a detected tone combination, said circuit comprising: a. a set of input terminals for receiving the set of digital signals, said set of input terminals corresponding in number and individual associations to said set of digital signals, b. a set of N tone combination detector gates, said set of detector gates corresponding in number and individual associations to a predetermined set of tone combinations, each detector gate of the set having a plurality of gate inputs connected to different input terminals of said set of input terminals, each detector gate of said set being operative to propogate an ASSERTION state to its output when an ASSERTION state is received at all of its gate inputs, c. output buffer means for providing a tone receiver output signal representing a detected tone combination of said predetermined set of combinations, d. means operatively connecting the outputs of the detector gates and the output buffer means, e. means for enabling the tone receiver output signal, said means for enabling the tone receiver output signal being operative to enable the same in response to presence of an ASSERTION state among the outputs of said set of detector gates, f. said set of N detector gates includes a predetermined subset of detector gates each of which has another gate input which is in addition to its plurality of gate inputs connected to input terminals, and g. the another gate input of each detector gate of the subset being commonly connected to an adjustable logic signal means, said adjustable logic signal means being of a type which may be adjusted from one condition in which it applies an ASSERTION state to the another gate inputs to another condition in which it applies a NEGATION state to the another gate inputs.
Claim 15
Dependent Claim
339 words
A digital tone receiver circuit for receiving a set of digital signals which when respectively in their ASSERTION state represent the detection of a respective tone of a corresponding predetermined set of tones, and for converting said digital signals into a tone receiver output signal representing a detected tone combination, said circuit comprising: a. a set of input terminals for receiving the set of digital signals, said set of input terminals corresponding in number and individual associations to said set of digital signals, b. a set of N tone combination detector gates, said set of detector gates corresponding in number and individual associations to a predetermined set of tone combinations, each detector gate of the set having a plurality of gate inputs connected to different input terminals of said set of input terminals, each detector gate of said set being operative to propogate an ASSERTION state to its output when an ASSERTION state is received at all of its gate inputs, c. output buffer means for providing a tone receiver output signal representing a detected tone combination of said predetermined set of combinations, d. means operatively connecting the outputs of the detector gates and the output buffer means, e. means for enabling the tone receiver output signal, said means for enabling the tone receiver output signal being operative to enable the same in response to presence of an ASSERTION state among the outputs of said set of detector gates, f. said set of N detector gates includes a predetermined subset of detector gates each of which has another gate input which is in addition to its plurality of gate inputs connected to input terminals, and g. the another gate input of each detector gate of the subset being commonly connected to an adjustable logic signal means, said adjustable logic signal means being of a type which may be adjusted from one condition in which it applies an ASSERTION state to the another gate inputs to another condition in which it applies a NEGATION state to the another gate inputs.
References Cited (Backward Citations)
US3537001A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-15 | 1981-02-14 | 1981-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-15 | 1985-02-14 | 1985-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-15 | 1989-02-14 | 1989-08-16 | $7700.00 | Window Closed / Lapsed |