US4042781A
Expired / Lapsed
US
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Apparatus for synchronizing oscillators in the network nodes of a digital telecommunications network
Assignee: Siemens AG
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Filing: 1976-07-23
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Granted: 1977-08-16
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Expires: 1996-07-23
Abstract
Abstract A circuit arrangement is disclosed for synchronizing the oscillators of a digital telecommunications network. The network nodes of a PCM t.d.m. telecommunications network contain mutually synchronizing exchange pulse train oscillators. In each of the network nodes, a first pulse sequence is formed from the line pulse trains of the digital telecommunications lines in accordance with a pulse train frequency reduction factor. A second pulse sequence is formed in each of the network nodes by the exchange pulse train oscillator in accordance with the pulse train frequency reduction factor. Phase discriminators formed by logic-linking circuits are individually assigned and connected to the digital telecommunications lines. Phase differences between the first pulse sequence associated with the line pulse train and the second pulse sequence associated with the relevant exchange pulse train are detected by the phase discriminator. These detected phase difference signals can be combined in a sum or mean value circuit. As a result of these phase difference signals, a frequency regulating signal is generated which regulates the frequency of the exchange pulse train oscillator in each of the network nodes. In the circuit arrangement of this invention, the phase discriminator signal is maintained within a constant zone on both sides of a linear range. Each overshooting and undershooting of a ± n2 πstage (n = 0, 1, 2, . . . N) of the phase difference between the first sequence (the line pulse train pulse sequence) and the second sequence (the exchange pulse train pulse sequence) is digitally counted in a counting device with a counting volume N. A first special control input of the phase discriminator receives a first special control input which maintains the phase discriminator in a starting state corresponding to a phase difference of +2π. This first special control signal is generated when the counting device indicates that the count of the overshooting of the +n2π stages exceeds the count of the undershooting of +n2π stages. In like manner, second special control input of the phase discriminator receives a second special control signal which maintains the phase discriminator in a starting state corresponding to a phase difference of -2π. This second special control signal is generated when the counting device indicates that the count of the undershooting of -n2π stages exceeds the count of the overshooting -n2π stages.
Inventors
- 👤 Alexander Dragotinov
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:14
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0676; C; C04; C04B; C04B14/00; C04B14/38; C04B14/48; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
446 words
A circuit for mutually snychronizing a plurality of exchange pulse train oscillators in a PCM t.d.m. digital telecommunications network wherein one of said exchange pulse train oscillators is arranged in each of the network nodes of said telecommunications network, said circuit comprising in each network node: a first frequency reducer connected to the incoming digital telecommunication lines for generating a first pulse sequence according to a given frequency reduction factor; said first pulse sequence corresponding to the line pulse train of said incoming digital telecommunication lines; a second frequency reducer connected to the output of said exchange pulse train oscillator for generating a second pulse sequence according to said given frequency reduction factor, said second pulse sequence corresponding to the exchange pulse train generated by said exchange pulse train oscillator; a phase discriminator connected to receive said first pulse sequence from said first frequency reducer and said second pulse sequence from said second frequency reducer, said phase discriminator comprising logic-linking circuits, whereby said phase discriminator generates a phase difference signal in response to the phase difference between said first pulse sequence and said second pulse sequence; means connected to said phase discriminator for generating a frequency regulating signal in response to the phase difference signal generated by said phase discriminator, whereby said frequency regulating signal is used to frequency regulate said exchange pulse train oscillator contained in said network node; means connected to said first and second frequency reducers for comparing said first and second pulse sequences and digitally counting each overshooting and each undershooting of a -n2π (n = 0, 1, 2, 3, . . . N) stage of the phase difference between said first pulse sequence and said second pulse sequence, said counting means having a counting volume N, said comparing and counting means providing said phase discriminator with a first special control input signal for maintaining said phase discriminator in a starting state corresponding to a phase difference of +2π and a second special control input signal for maintaining said phase discriminator in a starting state corresponding to a phase difference of -2π, said first special control signal being generated by said counting means when the count of the overshooting of +n2π stages of the phase difference exceeds the count of the undershooting of +n2π stages, said second special control signal being generated by said counting means when the count of the undershooting of -n2π stages of the phase difference exceeds the count of the overshooting of -n2π stages, whereby the output phase difference signal of said phase discriminator enables said means for generating a regulating signal to generate a regulating signal within a constant zone on both sides of a linear range.
Claim 2
Dependent Claim
446 words
A circuit for mutually snychronizing a plurality of exchange pulse train oscillators in a PCM t.d.m. digital telecommunications network wherein one of said exchange pulse train oscillators is arranged in each of the network nodes of said telecommunications network, said circuit comprising in each network node: a first frequency reducer connected to the incoming digital telecommunication lines for generating a first pulse sequence according to a given frequency reduction factor; said first pulse sequence corresponding to the line pulse train of said incoming digital telecommunication lines; a second frequency reducer connected to the output of said exchange pulse train oscillator for generating a second pulse sequence according to said given frequency reduction factor, said second pulse sequence corresponding to the exchange pulse train generated by said exchange pulse train oscillator; a phase discriminator connected to receive said first pulse sequence from said first frequency reducer and said second pulse sequence from said second frequency reducer, said phase discriminator comprising logic-linking circuits, whereby said phase discriminator generates a phase difference signal in response to the phase difference between said first pulse sequence and said second pulse sequence; means connected to said phase discriminator for generating a frequency regulating signal in response to the phase difference signal generated by said phase discriminator, whereby said frequency regulating signal is used to frequency regulate said exchange pulse train oscillator contained in said network node; means connected to said first and second frequency reducers for comparing said first and second pulse sequences and digitally counting each overshooting and each undershooting of a -n2π (n = 0, 1, 2, 3, . . . N) stage of the phase difference between said first pulse sequence and said second pulse sequence, said counting means having a counting volume N, said comparing and counting means providing said phase discriminator with a first special control input signal for maintaining said phase discriminator in a starting state corresponding to a phase difference of +2π and a second special control input signal for maintaining said phase discriminator in a starting state corresponding to a phase difference of -2π, said first special control signal being generated by said counting means when the count of the overshooting of +n2π stages of the phase difference exceeds the count of the undershooting of +n2π stages, said second special control signal being generated by said counting means when the count of the undershooting of -n2π stages of the phase difference exceeds the count of the overshooting of -n2π stages, whereby the output phase difference signal of said phase discriminator enables said means for generating a regulating signal to generate a regulating signal within a constant zone on both sides of a linear range.
Claim 3
Dependent Claim
131 words
A circuit according to claim 1 wherein said first and second frequency reducers have a frequency reduction ratio of 1:4 and said comparing and counting means further comprises: means for establishing the coincidence of the end and the beginning of individual pulse periods in each of four consecutive pulse periods of said first and second pulse sequences with in each case the beginning and end of a fourth pulse period of said first and second pulse sequences; means connected to said coincidence means for generating a counting pulse which indicates the overshooting and undershooting of a ±n2π stage of the phase difference; a counting device connected to said means for generating a counting pulse, whereby said counting device receives said counting pulse and sends an output signal to said phase discriminator.
Claim 4
Dependent Claim
269 words
A circuit according to claim 2 wherein said coincidence means further comprises: four logic-linking means (L201, L202, L203, L204) individually connected to said first and second frequency reduces in a manner which enables each of said logic-linking elements to be associated with a different one of said four consecutive pulse periods; means for combining said four logic-linking means in pairs, whereby each pair of said logic-linking elements provides one output signal; said means for generating a counting pulse further comprising: first and second 1-bit stores SU and SG each connected to receive one of said output signals from said combined logic-linking means, said 1-bit stores each being reset by said second pulse sequence; a first group of two further logic-linking means (EU and EG) one of which (EU) is connected to said first store (SU) and the other of which (EG) is connected to said second store (SG), said first group being alternately unlocked by said second frequency reducer for the duration of a pulse period of said second pulse sequence, whereby said first group generates a counting pulse which indicates the overshooting of a ±n2π stage of the phase difference; a second group of two further logic-linking means (AU and AG), one of which (AU) is connected to said first store (SU) and the other of which (AG) is connected to said second store (SG), said second group being alternately unlocked by said second frequency reducer for the duration of a pulse period of said second pulse sequence, whereby said second group generates a counting pulse which indicates the undershooting of a ±n2π stage of the phase difference.
Claim 5
Dependent Claim
149 words
A circuit according to claim 3 wherein said counting device is a forward-backwards counter (BZ) with two operating states and wherein said counting means further comprises a 1-bit control store connected to said forward-backwards counter for controlling the operating state of said forward-backwards counter, said 1-bit control store being switched over when the zero state of said forward-backwards counter is reached, whereby in said first operating state said counter is controlled in the forward direction by said counting pulse corresponding to the overshooting of a +n2π stage and in the backwards direction by said counting pulse corresponding to the undershooting of a +n2π l stage, and whereby in said second operating stage said counter is controlled in the forward direction by said counting pulse corresponding to the undershooting of a -n2π stage and in the backwards direction by said counting pulse corresponding to the overshooting of a -n2π stage.
Claim 6
Dependent Claim
34 words
A circuit according to claim 4 wherein said counting means further comprises a pulse suppression means for suppressing the subsequent like-directed one of said counting pulses whenever said forward-backwards counter reaches the zero state.
Claim 7
Dependent Claim
166 words
A circuit according to claim 1 wherein said counting and comparing means digitally counts each overshooting and each undershooting of a ±nπ(n = 1, 2, 3, . . . N) stage of the phase difference between said first pulse sequence and said second pulse sequence whereby said counting and comparing means provides said pulse discriminator with a first special control input signal for maintaining said phase discriminator in a starting state corresponding to a phase difference of +π and a second special control signal for maintaining said phase discriminator in a starting state corresponding to a phase difference of -π, said first special control signal being generated by said counting means when the count of the overshooting of +nπ stages of the phase difference exceeds the count of the undershooting of +nπ stages, said second special control signal being generated by said counting means when the count of the undershooting of -nπ stages of the phase difference exceeds the count of the overshooting of -nπ stages.
Claim 8
Dependent Claim
172 words
A circuit according to claim 1 wherein said counting and comparing means digitally counts each overshooting and each undershooting of a ±n π/2 (n = 1, 2, 3, . . . N) stage of the phase difference between said first pulse sequence and said second pulse sequence, whereby said counting and comparing means provides said phase discriminator with a first special control input signal for maintaining said phase discriminator in a starting state corresponding to a phase difference of +π/2 and a second special control signal for maintaining said phase discriminator in a starting state corresponding to a phase difference of -π/2, said first special control signal being generated by said counting means when the count of the overshooting of +n π/2 stages of the phase difference exceeds the count of the undershooting of +n π/2 stages, said second special control signal being generated by said counting means when the count of the undershooting of -n π/2 stages of the phase difference exceeds the count of the overshooting of -n π/2 stages.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-15 | 1981-02-14 | 1981-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-15 | 1985-02-14 | 1985-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-15 | 1989-02-14 | 1989-08-16 | $7700.00 | Window Closed / Lapsed |